diff options
| author | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-05-27 13:44:57 +0000 |
|---|---|---|
| committer | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-05-27 13:44:57 +0000 |
| commit | 8401eca859f413e6ec022f6e5dd61783c2b1d392 (patch) | |
| tree | cffea8179a610d43159f46aba2d7088c8ac16b3f /gcc/config/aarch64 | |
| parent | 29602b759d47dc27753fc23101e27e3907edabb9 (diff) | |
| download | gcc-8401eca859f413e6ec022f6e5dd61783c2b1d392.tar.gz | |
[AArch64] Tie operand 1 to operand 0 in AESMC pattern when AES/AESMC fusion is enabled
* config/aarch64/aarch64.c (aarch64_fusion_enabled_p): New function.
* config/aarch64/aarch64-protos.h (aarch64_fusion_enabled_p): Declare
prototype.
* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aesmc_op>v16qi):
Add "=w,0" alternative. Enable it when AES/AESMC fusion is enabled.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236820 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/aarch64')
| -rw-r--r-- | gcc/config/aarch64/aarch64-protos.h | 1 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 18 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 8 |
3 files changed, 24 insertions, 3 deletions
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 1b20cf9da9e..dcf1748d82f 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -287,6 +287,7 @@ bool aarch64_constant_address_p (rtx); bool aarch64_expand_movmem (rtx *); bool aarch64_float_const_zero_rtx_p (rtx); bool aarch64_function_arg_regno_p (unsigned); +bool aarch64_fusion_enabled_p (enum aarch64_fusion_pairs); bool aarch64_gen_movmemqi (rtx *); bool aarch64_gimple_fold_builtin (gimple_stmt_iterator *); bool aarch64_is_extend_from_extract (machine_mode, rtx, rtx); diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 3318c2155f5..fe1c22bfdf7 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5401,13 +5401,25 @@ [(set_attr "type" "crypto_aese")] ) +;; When AES/AESMC fusion is enabled we want the register allocation to +;; look like: +;; AESE Vn, _ +;; AESMC Vn, Vn +;; So prefer to tie operand 1 to operand 0 when fusing. + (define_insn "aarch64_crypto_aes<aesmc_op>v16qi" - [(set (match_operand:V16QI 0 "register_operand" "=w") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "w")] + [(set (match_operand:V16QI 0 "register_operand" "=w,w") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0,w")] CRYPTO_AESMC))] "TARGET_SIMD && TARGET_CRYPTO" "aes<aesmc_op>\\t%0.16b, %1.16b" - [(set_attr "type" "crypto_aesmc")] + [(set_attr "type" "crypto_aesmc") + (set_attr_alternative "enabled" + [(if_then_else (match_test + "aarch64_fusion_enabled_p (AARCH64_FUSE_AES_AESMC)") + (const_string "yes" ) + (const_string "no")) + (const_string "yes")])] ) ;; sha1 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 2315939ebfa..d2ac25ce339 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -13181,6 +13181,14 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr) return false; } +/* Return true iff the instruction fusion described by OP is enabled. */ + +bool +aarch64_fusion_enabled_p (enum aarch64_fusion_pairs op) +{ + return (aarch64_tune_params.fusible_ops & op) != 0; +} + /* If MEM is in the form of [base+offset], extract the two parts of address and set to BASE and OFFSET, otherwise return false after clearing BASE and OFFSET. */ |