* config/alpha/alpha.c (alpha_adjust_cost): Remove everything but

        memory latency adjustments.
        (alpha_variable_issue): Remove.
        (alpha_use_dfa_pipeline_interface): New.
        (alpha_multipass_dfa_lookahead): New.
        * config/alpha/alpha.md: Remove define_function_unit scheduling;
        include new dfa scheduling.
        (attr type): Add none.
        (blockage): Use it.
        * config/alpha/ev4.md: New.
        * config/alpha/ev5.md: New.
        * config/alpha/ev6.md: New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@53196 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 29 insertions, 127 deletions

diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 915d6e48996..c40636a4bb1 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -157,8 +157,10 @@ static int alpha_adjust_cost
   PARAMS ((rtx, rtx, rtx, int));
 static int alpha_issue_rate
   PARAMS ((void));
-static int alpha_variable_issue
-  PARAMS ((FILE *, int, rtx, int));
+static int alpha_use_dfa_pipeline_interface
+  PARAMS ((void));
+static int alpha_multipass_dfa_lookahead
+  PARAMS ((void));
 
 #if TARGET_ABI_UNICOSMK
 static void alpha_init_machine_status
@@ -231,8 +233,12 @@ static unsigned int unicosmk_section_type_flags PARAMS ((tree, const char *,
 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
 #undef TARGET_SCHED_ISSUE_RATE
 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
-#undef TARGET_SCHED_VARIABLE_ISSUE
-#define TARGET_SCHED_VARIABLE_ISSUE alpha_variable_issue
+#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
+  alpha_use_dfa_pipeline_interface
+#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
+#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
+  alpha_multipass_dfa_lookahead
 
 struct gcc_target targetm = TARGET_INITIALIZER;
 
@@ -4828,9 +4834,8 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
   /* If the dependence is an anti-dependence, there is no cost.  For an
      output dependence, there is sometimes a cost, but it doesn't seem
      worth handling those few cases.  */
-
   if (REG_NOTE_KIND (link) != 0)
-    return 0;
+    return cost;
 
   /* If we can't recognize the insns, we can't really do anything.  */
   if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
@@ -4845,122 +4850,13 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
       || dep_insn_type == TYPE_LDSYM)
     cost += alpha_memory_latency-1;
 
-  switch (alpha_cpu)
-    {
-    case PROCESSOR_EV4:
-      /* On EV4, if INSN is a store insn and DEP_INSN is setting the data
-	 being stored, we can sometimes lower the cost.  */
-
-      if ((insn_type == TYPE_IST || insn_type == TYPE_FST)
-	  && (set = single_set (dep_insn)) != 0
-	  && GET_CODE (PATTERN (insn)) == SET
-	  && rtx_equal_p (SET_DEST (set), SET_SRC (PATTERN (insn))))
-	{
-	  switch (dep_insn_type)
-	    {
-	    case TYPE_ILD:
-	    case TYPE_FLD:
-	      /* No savings here.  */
-	      return cost;
-
-	    case TYPE_IMUL:
-	      /* In these cases, we save one cycle.  */
-	      return cost - 1;
-
-	    default:
-	      /* In all other cases, we save two cycles.  */
-	      return MAX (0, cost - 2);
-	    }
-	}
+  /* Everything else handled in DFA bypasses now.  */
 
-      /* Another case that needs adjustment is an arithmetic or logical
-	 operation.  It's cost is usually one cycle, but we default it to
-	 two in the MD file.  The only case that it is actually two is
-	 for the address in loads, stores, and jumps.  */
-
-      if (dep_insn_type == TYPE_IADD || dep_insn_type == TYPE_ILOG)
-	{
-	  switch (insn_type)
-	    {
-	    case TYPE_ILD:
-	    case TYPE_IST:
-	    case TYPE_FLD:
-	    case TYPE_FST:
-	    case TYPE_JSR:
-	      return cost;
-	    default:
-	      return 1;
-	    }
-	}
-
-      /* The final case is when a compare feeds into an integer branch;
-	 the cost is only one cycle in that case.  */
-
-      if (dep_insn_type == TYPE_ICMP && insn_type == TYPE_IBR)
-	return 1;
-      break;
-
-    case PROCESSOR_EV5:
-      /* And the lord DEC saith:  "A special bypass provides an effective
-	 latency of 0 cycles for an ICMP or ILOG insn producing the test
-	 operand of an IBR or ICMOV insn." */
-
-      if ((dep_insn_type == TYPE_ICMP || dep_insn_type == TYPE_ILOG)
-	  && (set = single_set (dep_insn)) != 0)
-	{
-	  /* A branch only has one input.  This must be it.  */
-	  if (insn_type == TYPE_IBR)
-	    return 0;
-	  /* A conditional move has three, make sure it is the test.  */
-	  if (insn_type == TYPE_ICMOV
-	      && GET_CODE (set_src = PATTERN (insn)) == SET
-	      && GET_CODE (set_src = SET_SRC (set_src)) == IF_THEN_ELSE
-	      && rtx_equal_p (SET_DEST (set), XEXP (set_src, 0)))
-	    return 0;
-	}
-
-      /* "The multiplier is unable to receive data from IEU bypass paths.
-	 The instruction issues at the expected time, but its latency is
-	 increased by the time it takes for the input data to become
-	 available to the multiplier" -- which happens in pipeline stage
-	 six, when results are comitted to the register file.  */
-
-      if (insn_type == TYPE_IMUL)
-	{
-	  switch (dep_insn_type)
-	    {
-	    /* These insns produce their results in pipeline stage five.  */
-	    case TYPE_ILD:
-	    case TYPE_ICMOV:
-	    case TYPE_IMUL:
-	    case TYPE_MVI:
-	      return cost + 1;
-
-	    /* Other integer insns produce results in pipeline stage four.  */
-	    default:
-	      return cost + 2;
-	    }
-	}
-      break;
-
-    case PROCESSOR_EV6:
-      /* There is additional latency to move the result of (most) FP 
-         operations anywhere but the FP register file.  */
-
-      if ((insn_type == TYPE_FST || insn_type == TYPE_FTOI)
-	  && (dep_insn_type == TYPE_FADD ||
-	      dep_insn_type == TYPE_FMUL ||
-	      dep_insn_type == TYPE_FCMOV))
-        return cost + 2;
-
-      break;
-    }
-
-  /* Otherwise, return the default cost.  */
   return cost;
 }
 
-/* Function to initialize the issue rate used by the scheduler.  */
+/* The number of instructions that can be issued per cycle.  */
+
 static int
 alpha_issue_rate ()
 {
@@ -4968,18 +4864,24 @@ alpha_issue_rate ()
 }
 
 static int
-alpha_variable_issue (dump, verbose, insn, cim)
-     FILE *dump ATTRIBUTE_UNUSED;
-     int verbose ATTRIBUTE_UNUSED;
-     rtx insn;
-     int cim;
+alpha_use_dfa_pipeline_interface ()
 {
-    if (recog_memoized (insn) < 0 || get_attr_type (insn) == TYPE_MULTI)
-      return 0;
-
-    return cim - 1;
+  return true;
 }
 
+/* How many alternative schedules to try.  This should be as wide as the
+   scheduling freedom in the DFA, but no wider.  Making this value too
+   large results extra work for the scheduler.
+
+   For EV4, loads can be issued to either IB0 or IB1, thus we have 2
+   alternative schedules.  For EV5, we can choose between E0/E1 and
+   FA/FM.  For EV6, an arithmatic insn can be issued to U0/U1/L0/L1.  */
+
+static int
+alpha_multipass_dfa_lookahead ()
+{
+  return (alpha_cpu == PROCESSOR_EV6 ? 4 : 2);
+}
 
 /* Register global variables and machine-specific functions with the
    garbage collector.  */