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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2021-05-10 09:49:35 +0300 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@synopsys.com> | 2021-05-10 09:57:54 +0300 |
| commit | 79a27f32df8eab0add722f75332f78fe20d94da3 (patch) | |
| tree | 936182eb06c128b5851bbc371e3765926d32d62b /gcc/config/arc/arc.md | |
| parent | 09ae0f6c3ee0612012a67df4387d55efa19b8cad (diff) | |
| download | gcc-79a27f32df8eab0add722f75332f78fe20d94da3.tar.gz | |
arc: Improve vector support for ARCv2.
Add vector negate, reduc_plus_scal, vec_duplicate, vector
min/max/mult/div patterns. Besides vector negate and reduction
patterns, all the others are emulated using scalar instructions. The
reason is taking advantage of the double load/store instructions as
well as enabling the autovectorizer to further analize a loop.
gcc/
2021-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (UNSPEC_ARC_DMPYWH): Define.
* config/arc/simdext.md (VCT): Add predicates for iterator
elements.
(EMUVEC): Define.
(voptab): Likewise.
(vec_widen_<V_US>mult_hi_v4hi): Change pattern predicate.
(<voptab>v2si3): New patterns.
(neg): Likewise.
(reduc_plus_scal_v4hi): Likewise.
(reduc_plus_scal_v2si): Likewise.
(vec_duplicatev2si): Likewise.
(vec_duplicatev4hi): Likewise.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Diffstat (limited to 'gcc/config/arc/arc.md')
| -rw-r--r-- | gcc/config/arc/arc.md | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index f3efe65ca2f..b6f2d8e28be 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -128,6 +128,7 @@ UNSPEC_ARC_DMACHU UNSPEC_ARC_DMACWH UNSPEC_ARC_DMACWHU + UNSPEC_ARC_DMPYWH UNSPEC_ARC_QMACH UNSPEC_ARC_QMACHU UNSPEC_ARC_QMPYH |