2015-09-15 Christian Bruel <christian.bruel@st.com>

	PR target/52144
	* config/arm/arm.c (arm_option_params_internal): Remove opts parameter.
	* config/arm/arm-c.c (arm_cpu_builtins): Declare static.
	Remove flags parameter.
	* config/arm/arm.h (TARGET_32BIT_P, TARGET_ARM_QBIT_P)
	(TARGET_ARM_SAT_P, TARGET_IDIV_P, TARGET_HAVE_LDREX_P)
	(TARGET_HAVE_LDREXBH_P, TARGET_HAVE_LDREXD_P, TARGET_DSP_MULTIPLY_P)
	(TARGET_ARM_FEATURE_LDREX_P, TARGET_INT_SIMD_P): Redefine macros with...
	(TARGET_ARM_SAT, TARGET_IDIV, TARGET_HAVE_LDREX)
	(TARGET_HAVE_LDREXBH, TARGET_HAVE_LDREXD, TARGET_ARM_FEATURE_LDREX)
	(TARGET_DSP_MULTIPLY, TARGET_INT_SIMD): Redefined macros.
	* gcc/config/arm/arm-protos.h (arm_cpu_builtins): Remove declaration.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227795 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 14 insertions, 35 deletions

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index f7a9d638673..87c9f904894 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -160,8 +160,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
 #define TARGET_THUMB1			(TARGET_THUMB && !arm_arch_thumb2)
 /* Arm or Thumb-2 32-bit code.  */
 #define TARGET_32BIT			(TARGET_ARM || arm_arch_thumb2)
-#define TARGET_32BIT_P(flags)		(TARGET_ARM_P (flags) \
-					 || arm_arch_thumb2)
 /* 32-bit Thumb-2 code.  */
 #define TARGET_THUMB2			(TARGET_THUMB && arm_arch_thumb2)
 /* Thumb-1 only.  */
@@ -220,23 +218,18 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
   (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP			\
    && ARM_FPU_FSET_HAS (arm_fpu_desc->features, FPU_FL_NEON))
 
-
 /* Q-bit is present.  */
-#define TARGET_ARM_QBIT_P(flags) \
-  (TARGET_32BIT_P (flags) && arm_arch5e && (arm_arch_notm || arm_arch7))
-#define TARGET_ARM_QBIT TARGET_ARM_QBIT_P(target_flags)
+#define TARGET_ARM_QBIT \
+  (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
 /* Saturation operation, e.g. SSAT.  */
-#define TARGET_ARM_SAT_P(flags) \
-  (TARGET_32BIT_P (flags) && arm_arch6 && (arm_arch_notm || arm_arch7))
-#define TARGET_ARM_SAT TARGET_ARM_SAT_P(target_flags)
+#define TARGET_ARM_SAT \
+  (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7))
 /* "DSP" multiply instructions, eg. SMULxy.  */
-#define TARGET_DSP_MULTIPLY_P(flags) \
-  (TARGET_32BIT_P (flags) && arm_arch5e && (arm_arch_notm || arm_arch7em))
-#define TARGET_DSP_MULTIPLY TARGET_DSP_MULTIPLY_P(target_flags)
+#define TARGET_DSP_MULTIPLY \
+  (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
 /* Integer SIMD instructions, and extend-accumulate instructions.  */
-#define TARGET_INT_SIMD_P(flags) \
-  (TARGET_32BIT_P (flags) && arm_arch6 && (arm_arch_notm || arm_arch7em))
-#define TARGET_INT_SIMD TARGET_INT_SIMD_P(target_flags)
+#define TARGET_INT_SIMD \
+  (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
 
 /* Should MOVW/MOVT be used in preference to a constant pool.  */
 #define TARGET_USE_MOVT \
@@ -259,30 +252,21 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
 
 /* Nonzero if this chip supports ldrex and strex */
-#define TARGET_HAVE_LDREX_P(flags) ((arm_arch6 && TARGET_ARM_P (flags)) \
-				    || arm_arch7)
-#define TARGET_HAVE_LDREX	  TARGET_HAVE_LDREX_P (target_flags) 
+#define TARGET_HAVE_LDREX        ((arm_arch6 && TARGET_ARM) || arm_arch7)
 
 /* Nonzero if this chip supports ldrex{bh} and strex{bh}.  */
-#define TARGET_HAVE_LDREXBH_P(flags) ((arm_arch6k && TARGET_ARM_P (flags)) \
-				      || arm_arch7)
-#define TARGET_HAVE_LDREXBH	     TARGET_HAVE_LDREXBH_P (target_flags)
+#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
 
 /* Nonzero if this chip supports ldrexd and strexd.  */
-#define TARGET_HAVE_LDREXD_P(flags) (((arm_arch6k && TARGET_ARM_P (flags)) \
-				      || arm_arch7) && arm_arch_notm)
-#define TARGET_HAVE_LDREXD	    TARGET_HAVE_LDREXD_P (target_flags)
-				
+#define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \
+			     || arm_arch7) && arm_arch_notm)
 
 /* Nonzero if this chip supports load-acquire and store-release.  */
 #define TARGET_HAVE_LDACQ	(TARGET_ARM_ARCH >= 8)
 
 /* Nonzero if integer division instructions supported.  */
-#define TARGET_IDIV_P(flags)	((TARGET_ARM_P (flags) && arm_arch_arm_hwdiv) \
-				 || (TARGET_THUMB2_P (flags)                  \
-				     && arm_arch_thumb_hwdiv))
-#define TARGET_IDIV             TARGET_IDIV_P (target_flags)		
-
+#define TARGET_IDIV	((TARGET_ARM && arm_arch_arm_hwdiv)	\
+			 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
 
 /* Nonzero if disallow volatile memory access in IT block.  */
 #define TARGET_NO_VOLATILE_CE		(arm_arch_no_volatile_ce)
@@ -2220,11 +2204,6 @@ extern int making_const_table;
    | (TARGET_HAVE_LDREXBH ? 3 : 0)				\
    | (TARGET_HAVE_LDREXD ? 8 : 0))
 
-#define TARGET_ARM_FEATURE_LDREX_P(flags)			\
-  ((TARGET_HAVE_LDREX_P (flags) ? 4 : 0)			\
-   | (TARGET_HAVE_LDREXBH_P (flags) ? 3 : 0)			\
-   | (TARGET_HAVE_LDREXD_P (flags) ? 8 : 0))
-
 /* Set as a bit mask indicating the available widths of hardware floating
    point types.  Where bit 1 indicates 16-bit support, bit 2 indicates
    32-bit support, bit 3 indicates 64-bit support.  */