[AARCH64][Insn classification unification 3/N] ALU/shift types

2013-09-05  James Greenhalgh  <james.greenhalgh@arm.com>
	    Sofiane Naci  <sofiane.naci@arm.com>

	* config/arm/types.md (define_attr "type"):
	Expand "arlo_imm"
	into "adr", "alu_imm", "alus_imm", "logic_imm", "logics_imm".
	Expand "arlo_reg"
	into "adc_reg", "adc_imm", "adcs_reg", "adcs_imm", "alu_ext",
	"alu_reg", "alus_ext", "alus_reg", "bfm", "csel", "logic_reg",
	"logics_reg", "rev".
	Expand "arlo_shift"
	into "alu_shift_imm", "alus_shift_imm", "logic_shift_imm",
	"logics_shift_imm".
	Expand "arlo_shift_reg"
	into "alu_shift_reg", "alus_shift_reg", "logic_shift_reg",
	"logics_shift_reg".
	Expand "clz" into "clz, "rbit".
	Rename "shift" to "shift_imm".
	* config/arm/arm.md (define_attr "core_cycles"): Update for attribute
	changes.
	Update for attribute changes all occurrences of arlo_* and
	shift* types.
	* config/arm/arm-fixed.md: Update for attribute changes
	all occurrences of arlo_* types.
	* config/arm/thumb2.md: Update for attribute changes all occurrences
	of arlo_* types.
	* config/arm/arm.c (xscale_sched_adjust_cost):  (rtx insn, rtx
	(cortexa7_older_only): Likewise.
	(cortexa7_younger):  Likewise.
	* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
	(1020alu_shift_op): Likewise.
	(1020alu_shift_reg_op): Likewise.
	* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
	(alu_shift_op): Likewise.
	(alu_shift_reg_op): Likewise.
	* config/arm/arm1136jfs.md (11_alu_op): Update for
	attribute changes.
	(11_alu_shift_op): Likewise.
	(11_alu_shift_reg_op): Likewise.
	* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
	(9_alu_shift_reg_op): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_alu): Update for
	attribute changes.
	(cortex_a15_alu_shift): Likewise.
	(cortex_a15_alu_shift_reg): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_alu): Update for
	attribute changes.
	(cortex_a5_alu_shift): Likewise.
	* config/arm/cortex-a53.md
	(cortex_a53_alu): Update for attribute changes.
	(cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a7.md
	(cortex_a7_alu_imm): Update for attribute changes.
	(cortex_a7_alu_reg): Likewise.
	(cortex_a7_alu_shift): Likewise.
	* config/arm/cortex-a8.md
	(cortex_a8_alu): Update for attribute changes.
	(cortex_a8_alu_shift): Likewise.
	(cortex_a8_alu_shift_reg): Likewise.
	* config/arm/cortex-a9.md
	(cortex_a9_dp): Update for attribute changes.
	(cortex_a9_dp_shift): Likewise.
	* config/arm/cortex-m4.md
	(cortex_m4_alu): Update for attribute changes.
	* config/arm/cortex-r4.md
	(cortex_r4_alu): Update for attribute changes.
	(cortex_r4_mov): Likewise.
	(cortex_r4_alu_shift_reg): Likewise.
	* config/arm/fa526.md
	(526_alu_op): Update for attribute changes.
	(526_alu_shift_op): Likewise.
	* config/arm/fa606te.md
	(606te_alu_op): Update for attribute changes.
	* config/arm/fa626te.md
	(626te_alu_op): Update for attribute changes.
	(626te_alu_shift_op): Likewise.
	* config/arm/fa726te.md
	(726te_alu_op): Update for attribute changes.
	(726te_alu_shift_op): Likewise.
	(726te_alu_shift_reg_op): Likewise.
	* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
	(mp626_alu_shift_op): Likewise.
	* config/arm/marvell-pj4.md (pj4_alu): Update for attribute changes.
	(pj4_alu_conds): Likewise.
	(pj4_shift): Likewise.
	(pj4_shift_conds): Likewise.
	(pj4_alu_shift): Likewise.
	(pj4_alu_shift_conds): Likewise.
	* config/aarch64/aarch64.md: Update for attribute change
	all occurrences of arlo_* and shift* types.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@202291 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 11 insertions, 3 deletions

diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md
index 9112122d67b..6f4a8fa76e1 100644
--- a/gcc/config/arm/arm1026ejs.md
+++ b/gcc/config/arm/arm1026ejs.md
@@ -66,14 +66,20 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "alu_op" 1 
  (and (eq_attr "tune" "arm1026ejs")
-      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_reg,alus_reg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg,\
                        mov_imm,mov_reg,mvn_imm,mvn_reg"))
  "a_e,a_m,a_w")
 
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "alu_shift_op" 1 
  (and (eq_attr "tune" "arm1026ejs")
-      (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
+      (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm,\
+                       extend,mov_shift,mvn_shift"))
  "a_e,a_m,a_w")
 
 ;; ALU operations with a shift-by-register operand
@@ -82,7 +88,9 @@
 ;; the execute stage.
 (define_insn_reservation "alu_shift_reg_op" 2 
  (and (eq_attr "tune" "arm1026ejs")
-      (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+      (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
+                       mov_shift_reg,mvn_shift_reg"))
  "a_e*2,a_m,a_w")
 
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