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authorrearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>2012-03-20 14:11:05 +0000
committerrearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>2012-03-20 14:11:05 +0000
commit1987d213e18b11c0acf6e7d04033f4ca2e3e2c8a (patch)
tree4c93d29c94307b6e4e3429115aef44303c37b4ad /gcc/config/arm/predicates.md
parent32a4d55a791ca2b14d12ea480d841cd19531b131 (diff)
downloadgcc-1987d213e18b11c0acf6e7d04033f4ca2e3e2c8a.tar.gz
* arm/predicates.md (zero_operand, reg_or_zero_operand): New predicates.
* arm/neon.md (neon_vceq<mode>, neon_vcge<mode>): Use reg_or_zero_operand predicate. (neon_vcle<mode>, neon_vclt<mode>): Use zero_operand predicate. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@185573 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/arm/predicates.md')
-rw-r--r--gcc/config/arm/predicates.md9
1 files changed, 9 insertions, 0 deletions
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index dea3a96368e..9171d7377fe 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -89,6 +89,15 @@
&& REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
})
+(define_predicate "zero_operand"
+ (and (match_code "const_int,const_double,const_vector")
+ (match_test "op == CONST0_RTX (mode)")))
+
+;; Match a register, or zero in the appropriate mode.
+(define_predicate "reg_or_zero_operand"
+ (ior (match_operand 0 "s_register_operand")
+ (match_operand 0 "zero_operand")))
+
(define_special_predicate "subreg_lowpart_operator"
(and (match_code "subreg")
(match_test "subreg_lowpart_p (op)")))