* cfglayout.c, config/arm/arm.c, config/arm/cortex-a8.md,

	config/arm/neon-schedgen.ml, config/arm/neon.ml,
	config/arm/vec-common.md, config/ia64/div.md, cselib.c,
	df-core.c, df.h, dominance.c, optabs.c, opts.c, reg-stack.c,
	regstat.c, target.h, tree-ssa-live.c, tree-ssa-pre.c,
	tree-vect-transform.c, tree.def: Fix comment typos.  Follow
	spelling conventions.
	* doc/invoke.texi: Follow spelling conventions.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@127030 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 10 insertions, 10 deletions

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 47f33945036..6424498f2cf 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -6083,7 +6083,7 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse,
     {
       unsigned HOST_WIDE_INT imm = 0;
 
-      /* Un-invert bytes of recognized vector, if neccessary.  */
+      /* Un-invert bytes of recognized vector, if necessary.  */
       if (invmask != 0)
         for (i = 0; i < idx; i++)
           bytes[i] ^= invmask;
@@ -6212,7 +6212,7 @@ neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode,
     }
 }
 
-/* Initialise a vector with non-constant elements.  FIXME: We can do better
+/* Initialize a vector with non-constant elements.  FIXME: We can do better
    than the current implementation (building a vector on the stack and then
    loading it) in many cases.  See rs6000.c.  */
 
@@ -12664,7 +12664,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
       break;
 
     /* %# is a "break" sequence. It doesn't output anything, but is used to
-       seperate e.g. operand numbers from following text, if that text consists
+       separate e.g. operand numbers from following text, if that text consists
        of further digits which we don't want to be part of the operand
        number.  */
     case '#':
diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md
index 69d44de5720..e8ff16298c9 100644
--- a/gcc/config/arm/cortex-a8.md
+++ b/gcc/config/arm/cortex-a8.md
@@ -129,7 +129,7 @@
                "arm_no_early_alu_shift_value_dep")
 
 ;; Multiplication instructions.  These are categorized according to their
-;; reservation behaviour and the need below to distinguish certain
+;; reservation behavior and the need below to distinguish certain
 ;; varieties for bypasses.  Results are available at the E5 stage
 ;; (but some of these are multi-cycle instructions which explains the
 ;; latencies below).
@@ -245,7 +245,7 @@
 ;; reads the value to be stored at the start of E3 and the ALU insn
 ;; writes it at the end of E2.  Move instructions actually produce the
 ;; result at the end of E1, but since we don't have delay slots, the
-;; scheduling behaviour will be the same.
+;; scheduling behavior will be the same.
 (define_bypass 0 "cortex_a8_alu,cortex_a8_alu_shift,\
                   cortex_a8_alu_shift_reg,cortex_a8_mov"
                "cortex_a8_store1_2,cortex_a8_store3_4"
diff --git a/gcc/config/arm/neon-schedgen.ml b/gcc/config/arm/neon-schedgen.ml
index b47a0ae7d3c..c1094e9b038 100644
--- a/gcc/config/arm/neon-schedgen.ml
+++ b/gcc/config/arm/neon-schedgen.ml
@@ -63,7 +63,7 @@ type availability = Source of int
 
 type guard = Guard_none | Guard_only_m | Guard_only_n | Guard_only_d
 
-(* Reservation behaviours.  All but the last row here correspond to one
+(* Reservation behaviors.  All but the last row here correspond to one
    pipeline each.  Each constructor will correspond to one
    define_reservation.  *)
 type reservation =
@@ -78,7 +78,7 @@ type reservation =
 | Fmul_then_fadd | Fmul_then_fadd_2
 
 (* This table must be kept as short as possible by conflating
-   entries with the same availability behaviour.
+   entries with the same availability behavior.
 
    First components: instruction group names
    Second components: availability requirements, in the order in which
diff --git a/gcc/config/arm/neon.ml b/gcc/config/arm/neon.ml
index 59f6cc98579..39807a48d37 100644
--- a/gcc/config/arm/neon.ml
+++ b/gcc/config/arm/neon.ml
@@ -177,7 +177,7 @@ type opcode =
   (* Set/extract lanes from a vector.  *)
   | Vget_lane
   | Vset_lane
-  (* Initialise vector from bit pattern.  *)
+  (* Initialize vector from bit pattern.  *)
   | Vcreate
   (* Set all lanes to same value.  *)
   | Vdup_n
@@ -227,7 +227,7 @@ type features =
        names.  *)
   | Instruction_name of string list
     (* Mark that the intrinsic yields no instructions, or expands to yield
-       behaviour that the test generator cannot test.  *)
+       behavior that the test generator cannot test.  *)
   | No_op
     (* Mark that the intrinsic has constant arguments that cannot be set
        to the defaults (zero for pointers and one otherwise) in the test
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 0514b81e55c..9d576ab51f9 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -42,7 +42,7 @@
 })
 
 ;; Vector arithmetic. Expanders are blank, then unnamed insns implement
-;; patterns seperately for IWMMXT and Neon.
+;; patterns separately for IWMMXT and Neon.
 
 (define_expand "add<mode>3"
   [(set (match_operand:VALL 0 "s_register_operand" "")