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author | jakub <jakub@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-08-23 15:51:45 +0000 |
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committer | jakub <jakub@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-08-23 15:51:45 +0000 |
commit | 011b255e191b9476df47cdbb81cc27ad4c5a227e (patch) | |
tree | 62fb2f1d429ec029087fc74ce2fd3609e593cd39 /gcc/config/bfin | |
parent | 21a3e03414719df5ce8d78555cfb575dcc8d22c7 (diff) | |
download | gcc-011b255e191b9476df47cdbb81cc27ad4c5a227e.tar.gz |
PR middle-end/50161
* simplify-rtx.c (simplify_const_unary_operation): If
op is CONST_INT, don't look at op_mode, but use instead
mode.
* optabs.c (add_equal_note): For FFS, CLZ, CTZ,
CLRSB, POPCOUNT, PARITY and BSWAP use operand mode for
operation and TRUNCATE/ZERO_EXTEND if needed.
* doc/rtl.texi (ffs, clrsb, clz, ctz, popcount, parity, bswap):
Document that operand mode must be same as operation mode,
or VOIDmode.
* config/avr/avr.md (paritysi2, *parityqihi2.libgcc,
*paritysihi2.libgcc, popcountsi2, *popcountsi2.libgcc,
*popcountqihi2.libgcc, clzsi2, *clzsihi2.libgcc, ctzsi2,
*ctzsihi2.libgcc, ffssi2, *ffssihi2.libgcc): For unary ops
use the mode of operand for the operation and add truncate
or zero_extend around if needed.
* config/c6x/c6x.md (ctzdi2): Likewise.
* config/bfin/bfin.md (clrsbsi2, signbitssi2): Likewise.
* gcc.dg/pr50161.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@177991 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/bfin')
-rw-r--r-- | gcc/config/bfin/bfin.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md index 8d8413de304..9c8d4c26d3e 100644 --- a/gcc/config/bfin/bfin.md +++ b/gcc/config/bfin/bfin.md @@ -1,5 +1,5 @@ ;;- Machine description for Blackfin for GNU compiler -;; Copyright 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +;; Copyright 2005, 2006, 2007, 2008, 2011 Free Software Foundation, Inc. ;; Contributed by Analog Devices. ;; This file is part of GCC. @@ -1463,7 +1463,7 @@ (define_expand "clrsbsi2" [(set (match_dup 2) - (clrsb:HI (match_operand:SI 1 "register_operand" "d"))) + (truncate:HI (clrsb:SI (match_operand:SI 1 "register_operand" "d")))) (set (match_operand:SI 0 "register_operand") (zero_extend:SI (match_dup 2)))] "" @@ -1473,7 +1473,7 @@ (define_insn "signbitssi2" [(set (match_operand:HI 0 "register_operand" "=d") - (clrsb:HI (match_operand:SI 1 "register_operand" "d")))] + (truncate:HI (clrsb:SI (match_operand:SI 1 "register_operand" "d"))))] "" "%h0 = signbits %1%!" [(set_attr "type" "dsp32")]) |