* config/alpha/alpha.md (umk_mismatch_args): Don't put a mode on set.

	* config/fr30/fr30.md: Likweise
	(movsi_push): Likewise.
	(movsi_pop): Likewise.
	(enter_func): Likewise.
	* config/moxie/moxie.md (movsi_push): Likewise.
	(movsi_pop): Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@168817 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 82 insertions, 82 deletions

diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
index afab0512d62..f95559f3d46 100644
--- a/gcc/config/fr30/fr30.md
+++ b/gcc/config/fr30/fr30.md
@@ -140,16 +140,16 @@
 
 ;; Push a register onto the stack
 (define_insn "movsi_push"
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "register_operand" "a"))]
+  [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 0 "register_operand" "a"))]
   ""
   "st	%0, @-r15"
 )
 
 ;; Pop a register off the stack
 (define_insn "movsi_pop"
-  [(set:SI (match_operand:SI 0 "register_operand" "=a")
-	   (mem:SI (post_inc:SI (reg:SI 15))))]
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(mem:SI (post_inc:SI (reg:SI 15))))]
   ""
   "ld	@r15+, %0"
 )
@@ -292,8 +292,8 @@
    "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128
     && (GET_CODE (operands[0]) != SUBREG
 	|| SCALAR_INT_MODE_P (GET_MODE (XEXP (operands[0], 0))))"
-   [(set:SI (match_dup 0) (match_dup 1))
-    (set:SI (match_dup 0) (sign_extend:SI (match_dup 2)))]
+   [(set (match_dup 0) (match_dup 1))
+    (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
    "{
    operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
    operands[2] = gen_lowpart (QImode, operands[0]);
@@ -307,8 +307,8 @@
   [(set (match_operand:SI 0 "register_operand"  "")
 	(match_operand:SI 1 "const_int_operand" ""))]
    "(INTVAL (operands[1]) < 0) && ((INTVAL (operands[1]) & 0x00ffffff) == 0)"
-   [(set:SI (match_dup 0) (match_dup 2))
-    (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24)))
+   [(set (match_dup 0) (match_dup 2))
+    (parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 24)))
 	       (clobber (reg:CC 16))])]
    "{
    HOST_WIDE_INT val = INTVAL (operands[1]);
@@ -325,8 +325,8 @@
 	(match_operand:SI 1 "const_int_operand" ""))]
    "(INTVAL (operands[1]) > 0x00ffffff)
    && ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)"
-   [(set:SI (match_dup 0) (match_dup 2))
-    (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))
+   [(set (match_dup 0) (match_dup 2))
+    (parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))
 	       (clobber (reg:CC 16))])]
    "{
    HOST_WIDE_INT val = INTVAL (operands[1]);
@@ -417,108 +417,108 @@
 ;; is during function prologues and epilogues.
 
 (define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 2 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 3 "high_register_operand" "h"))]
+  [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 0 "high_register_operand" "h"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 1 "high_register_operand" "h"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 2 "high_register_operand" "h"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 3 "high_register_operand" "h"))]
   "fr30_check_multiple_regs (operands, 4, 1)"
   "stm1	(%0, %1, %2, %3)"
   [(set_attr "delay_type" "other")]
 )
 
 (define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 2 "high_register_operand" "h"))]
+  [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 0 "high_register_operand" "h"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 1 "high_register_operand" "h"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 2 "high_register_operand" "h"))]
   "fr30_check_multiple_regs (operands, 3, 1)"
   "stm1	(%0, %1, %2)"
   [(set_attr "delay_type" "other")]
 )
 
 (define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "high_register_operand" "h"))]
+  [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 0 "high_register_operand" "h"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 1 "high_register_operand" "h"))]
   "fr30_check_multiple_regs (operands, 2, 1)"
   "stm1	(%0, %1)"
   [(set_attr "delay_type" "other")]
 )
 
 (define_peephole
-  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 1 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 2 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 3 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))]
+  [(set (match_operand:SI 0 "high_register_operand" "h")
+	(mem:SI (post_inc:SI (reg:SI 15))))
+   (set (match_operand:SI 1 "high_register_operand" "h")
+	(mem:SI (post_inc:SI (reg:SI 15))))
+   (set (match_operand:SI 2 "high_register_operand" "h")
+	(mem:SI (post_inc:SI (reg:SI 15))))
+   (set (match_operand:SI 3 "high_register_operand" "h")
+	(mem:SI (post_inc:SI (reg:SI 15))))]
   "fr30_check_multiple_regs (operands, 4, 0)"
   "ldm1	(%0, %1, %2, %3)"
   [(set_attr "delay_type" "other")]
 )
 
 (define_peephole
-  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 1 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 2 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))]
+  [(set (match_operand:SI 0 "high_register_operand" "h")
+	(mem:SI (post_inc:SI (reg:SI 15))))
+   (set (match_operand:SI 1 "high_register_operand" "h")
+	(mem:SI (post_inc:SI (reg:SI 15))))
+   (set (match_operand:SI 2 "high_register_operand" "h")
+	(mem:SI (post_inc:SI (reg:SI 15))))]
   "fr30_check_multiple_regs (operands, 3, 0)"
   "ldm1	(%0, %1, %2)"
   [(set_attr "delay_type" "other")]
 )
 
 (define_peephole
-  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 1 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))]
+  [(set (match_operand:SI 0 "high_register_operand" "h")
+	(mem:SI (post_inc:SI (reg:SI 15))))
+   (set (match_operand:SI 1 "high_register_operand" "h")
+	(mem:SI (post_inc:SI (reg:SI 15))))]
   "fr30_check_multiple_regs (operands, 2, 0)"
   "ldm1	(%0, %1)"
   [(set_attr "delay_type" "other")]
 )
 
 (define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 2 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 3 "low_register_operand" "l"))]
+  [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 0 "low_register_operand" "l"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 1 "low_register_operand" "l"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 2 "low_register_operand" "l"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 3 "low_register_operand" "l"))]
   "fr30_check_multiple_regs (operands, 4, 1)"
   "stm0	(%0, %1, %2, %3)"
   [(set_attr "delay_type" "other")]
 )
 
 (define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 2 "low_register_operand" "l"))]
+  [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 0 "low_register_operand" "l"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 1 "low_register_operand" "l"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 2 "low_register_operand" "l"))]
   "fr30_check_multiple_regs (operands, 3, 1)"
   "stm0	(%0, %1, %2)"
   [(set_attr "delay_type" "other")]
 )
 
 (define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "low_register_operand" "l"))]
+  [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 0 "low_register_operand" "l"))
+   (set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 1 "low_register_operand" "l"))]
   "fr30_check_multiple_regs (operands, 2, 1)"
   "stm0	(%0, %1)"
   [(set_attr "delay_type" "other")]
@@ -1210,15 +1210,15 @@
 
 (define_expand "enter_func"
   [(parallel
-  [(set:SI (mem:SI (minus:SI (match_dup 1)
-			     (const_int 4)))
-	   (match_dup 2))
-   (set:SI (match_dup 2)
-	   (minus:SI (match_dup 1)
-		     (const_int 4)))
-   (set:SI (match_dup 1)
-	   (minus:SI (match_dup 1)
-		     (match_operand:SI 0 "immediate_operand")))]
+  [(set (mem:SI (minus:SI (match_dup 1)
+			  (const_int 4)))
+	(match_dup 2))
+   (set (match_dup 2)
+	(minus:SI (match_dup 1)
+		  (const_int 4)))
+   (set (match_dup 1)
+	(minus:SI (match_dup 1)
+		  (match_operand:SI 0 "immediate_operand")))]
   )]
   ""
 {
@@ -1227,15 +1227,15 @@
 })
 
 (define_insn "*enter_func"
-  [(set:SI (mem:SI (minus:SI (reg:SI 15)
-			     (const_int 4)))
-	   (reg:SI 14))
-   (set:SI (reg:SI 14)
-	   (minus:SI (reg:SI 15)
-		     (const_int 4)))
-   (set:SI (reg:SI 15)
-	   (minus:SI (reg:SI 15)
-		     (match_operand 0 "immediate_operand" "i")))]
+  [(set (mem:SI (minus:SI (reg:SI 15)
+			  (const_int 4)))
+	(reg:SI 14))
+   (set (reg:SI 14)
+	(minus:SI (reg:SI 15)
+		  (const_int 4)))
+   (set (reg:SI 15)
+	(minus:SI (reg:SI 15)
+		  (match_operand 0 "immediate_operand" "i")))]
   "reload_completed"
   "enter	#%0"
   [(set_attr "delay_type" "other")]