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| author | kazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-12-26 18:45:04 +0000 |
|---|---|---|
| committer | kazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-12-26 18:45:04 +0000 |
| commit | fcbfedc77e5d31d0dcbfdfc2050f12331c1faf20 (patch) | |
| tree | 693c752cca293a18b8a5f441753970e2faa97ce8 /gcc/config/i386/athlon.md | |
| parent | 2df457620208e53ee3febc057463e5b20fc7d085 (diff) | |
| download | gcc-fcbfedc77e5d31d0dcbfdfc2050f12331c1faf20.tar.gz | |
* config/i386/athlon.md: Fix comment typos.
* config/i386/crtdll.h: Likewise.
* config/i386/djgpp.h: Likewise.
* config/i386/i386-interix.h: Likewise.
* config/i386/i386.c: Likewise.
* config/i386/i386.h: Likewise.
* config/i386/i386.md: Likewise.
* config/i386/k6.md: Likewise.
* config/i386/mingw32.h: Likewise.
* config/i386/pentium.md: Likewise.
* config/i386/sco5.h: Likewise.
* config/i386/winnt.c: Likewise.
* config/i386/xmmintrin.h: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@60524 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386/athlon.md')
| -rw-r--r-- | gcc/config/i386/athlon.md | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/config/i386/athlon.md b/gcc/config/i386/athlon.md index 719046fcd61..6913fcd8bf4 100644 --- a/gcc/config/i386/athlon.md +++ b/gcc/config/i386/athlon.md @@ -53,7 +53,7 @@ ;; is used (this is needed to allow troughput of 1.5 double decoded ;; instructions per cycle). ;; -;; In order to avoid dependnece between reservation of decoder +;; In order to avoid dependence between reservation of decoder ;; and other units, we model decoder as two stage fully pipelined unit ;; and only double decoded instruction may occupy unit in the first cycle. ;; With this scheme however two double instructions can be issued cycle0. @@ -74,7 +74,7 @@ | (nothing,(athlon-decode0 + athlon-decode1)) | (nothing,(athlon-decode1 + athlon-decode2)))") -;; Agu and ieu unit results in extremly large automatons and +;; Agu and ieu unit results in extremely large automatons and ;; in our approximation they are hardly filled in. Only ieu ;; unit can, as issue rate is 3 and agu unit is always used ;; first in the insn reservations. Skip the models. @@ -107,7 +107,7 @@ (define_reservation "athlon-faddmul" "(athlon-fadd | athlon-fmul)") -;; Jump instructions are executed in the branch unit compltetely transparent to us +;; Jump instructions are executed in the branch unit completely transparent to us (define_insn_reservation "athlon_branch" 0 (and (eq_attr "cpu" "athlon,k8") (eq_attr "type" "ibr")) @@ -474,7 +474,7 @@ (and (eq_attr "cpu" "athlon,k8") (eq_attr "unit" "mmx")) "athlon-direct,athlon-faddmul") -;; SSE operations are handled by the i387 unit as well. The latnecy +;; SSE operations are handled by the i387 unit as well. The latency ;; is same as for i387 operations for scalar operations (define_insn_reservation "athlon_sselog_load" 6 (and (eq_attr "cpu" "athlon") |