2008-10-07 H.J. Lu <hongjiu.lu@intel.com>

	* config/i386/i386-protos.h (ix86_schedule): New.

	* config/i386/i386.c (ix86_schedule): New.
	(override_options): Add schedule to processor_alias_table.  Set
	ix86_schedule from the schedule field in processor_alias_table.
	(ix86_function_specific_save): Save ix86_schedule.
	(ix86_function_specific_restore): Restore ix86_schedule.

	* config/i386/i386.md (cpu): Map to ix86_schedule instead of
	ix86_tune.  Add none and remove i386, i486, pentium4, nocona
	and generic32.

	* config/i386/i386.opt: Add schedule.

	* config/i386/ppro.md: Remove generic32.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@140954 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 85 insertions, 85 deletions

diff --git a/gcc/config/i386/ppro.md b/gcc/config/i386/ppro.md
index b971e51089e..81c0746ea1e 100644
--- a/gcc/config/i386/ppro.md
+++ b/gcc/config/i386/ppro.md
@@ -135,25 +135,25 @@
 ;; on decoder 0, and say that it takes a little while before the result
 ;; is available.
 (define_insn_reservation "ppro_complex_insn" 6
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (eq_attr "type" "other,multi,call,callv,str"))
 			 "decoder0")
 
 ;; imov with memory operands does not use the integer units.
 (define_insn_reservation "ppro_imov" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "imov")))
 			 "decodern,(p0|p1)")
 
 (define_insn_reservation "ppro_imov_load" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "imov")))
 			 "decodern,p2")
 
 (define_insn_reservation "ppro_imov_store" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "store")
 				   (eq_attr "type" "imov")))
 			 "decoder0,p4+p3")
@@ -161,20 +161,20 @@
 ;; imovx always decodes to one uop, and also doesn't use the integer
 ;; units if it has memory operands.
 (define_insn_reservation "ppro_imovx" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "imovx")))
 			 "decodern,(p0|p1)")
 
 (define_insn_reservation "ppro_imovx_load" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "imovx")))
 			 "decodern,p2")
 
 ;; lea executes on port 0 with latency one and throughput 1.
 (define_insn_reservation "ppro_lea" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "lea")))
 			 "decodern,p0")
@@ -183,13 +183,13 @@
 ;; The load and store units need to be reserved when memory operands
 ;; are involved.
 (define_insn_reservation "ppro_shift_rotate" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
 			 "decodern,p0")
 
 (define_insn_reservation "ppro_shift_rotate_mem" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "!none")
 				   (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
 			 "decoder0,p2+p0,p4+p3")
@@ -213,32 +213,32 @@
 ;; results because we can assume these instructions can decode on all
 ;; decoders.
 (define_insn_reservation "ppro_branch" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "ibr")))
 			 "decodern,p1")
 
 ;; ??? Indirect branches probably have worse latency than this.
 (define_insn_reservation "ppro_indirect_branch" 6
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "!none")
 				   (eq_attr "type" "ibr")))
 			 "decoder0,p2+p1")
 
 (define_insn_reservation "ppro_leave" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (eq_attr "type" "leave"))
 			 "decoder0,p2+(p0|p1),(p0|p1)")
 
 ;; imul has throughput one, but latency 4, and can only execute on port 0.
 (define_insn_reservation "ppro_imul" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "imul")))
 			 "decodern,p0")
 
 (define_insn_reservation "ppro_imul_mem" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "!none")
 				   (eq_attr "type" "imul")))
 			 "decoder0,p2+p0")
@@ -247,42 +247,42 @@
 ;; QI, HI, and SI have issue latency 12, 21, and 37, respectively.
 ;; These issue latencies are modelled via the ppro_div automaton.
 (define_insn_reservation "ppro_idiv_QI" 19
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "QI")
 					(eq_attr "type" "idiv"))))
 			 "decoder0,(p0+idiv)*2,(p0|p1)+idiv,idiv*9")
 
 (define_insn_reservation "ppro_idiv_QI_load" 19
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "QI")
 					(eq_attr "type" "idiv"))))
 			 "decoder0,p2+p0+idiv,p0+idiv,(p0|p1)+idiv,idiv*9")
 
 (define_insn_reservation "ppro_idiv_HI" 23
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "HI")
 					(eq_attr "type" "idiv"))))
 			 "decoder0,(p0+idiv)*3,(p0|p1)+idiv,idiv*17")
 
 (define_insn_reservation "ppro_idiv_HI_load" 23
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "HI")
 					(eq_attr "type" "idiv"))))
 			 "decoder0,p2+p0+idiv,p0+idiv,(p0|p1)+idiv,idiv*18")
 
 (define_insn_reservation "ppro_idiv_SI" 39
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SI")
 					(eq_attr "type" "idiv"))))
 			 "decoder0,(p0+idiv)*3,(p0|p1)+idiv,idiv*33")
 
 (define_insn_reservation "ppro_idiv_SI_load" 39
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "SI")
 					(eq_attr "type" "idiv"))))
@@ -293,85 +293,85 @@
 ;;     has throughput "1/cycle (align with FADD)".  What do they
 ;;     mean and how can we model that?
 (define_insn_reservation "ppro_fop" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none,unknown")
 				   (eq_attr "type" "fop")))
 			 "decodern,p0")
 
 (define_insn_reservation "ppro_fop_load" 5
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "fop")))
 			 "decoder0,p2+p0,p0")
 
 (define_insn_reservation "ppro_fop_store" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "store")
 				   (eq_attr "type" "fop")))
 			 "decoder0,p0,p0,p0+p4+p3")
 
 (define_insn_reservation "ppro_fop_both" 5
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "both")
 				   (eq_attr "type" "fop")))
 			 "decoder0,p2+p0,p0+p4+p3")
 
 (define_insn_reservation "ppro_fsgn" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (eq_attr "type" "fsgn"))
 			 "decodern,p0")
 
 (define_insn_reservation "ppro_fistp" 5
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (eq_attr "type" "fistp"))
 			 "decoder0,p0*2,p4+p3")
 
 (define_insn_reservation "ppro_fcmov" 2
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (eq_attr "type" "fcmov"))
 			 "decoder0,p0*2")
 
 (define_insn_reservation "ppro_fcmp" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "fcmp")))
 			 "decodern,p0")
 
 (define_insn_reservation "ppro_fcmp_load" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "fcmp")))
 			 "decoder0,p2+p0")
 
 (define_insn_reservation "ppro_fmov" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "fmov")))
 			 "decodern,p0")
 
 (define_insn_reservation "ppro_fmov_load" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "!XF")
 					(eq_attr "type" "fmov"))))
 			 "decodern,p2")
 
 (define_insn_reservation "ppro_fmov_XF_load" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "XF")
 					(eq_attr "type" "fmov"))))
 			 "decoder0,(p2+p0)*2")
 
 (define_insn_reservation "ppro_fmov_store" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "store")
 				   (and (eq_attr "mode" "!XF")
 					(eq_attr "type" "fmov"))))
 			 "decodern,p0")
 
 (define_insn_reservation "ppro_fmov_XF_store" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "store")
 				   (and (eq_attr "mode" "XF")
 					(eq_attr "type" "fmov"))))
@@ -380,13 +380,13 @@
 ;; fmul executes on port 0 with latency 5.  It has issue latency 2,
 ;; but we don't model this.
 (define_insn_reservation "ppro_fmul" 5
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "fmul")))
 			 "decoder0,p0*2")
 
 (define_insn_reservation "ppro_fmul_load" 6
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "fmul")))
 			 "decoder0,p2+p0,p0")
@@ -397,42 +397,42 @@
 ;; that.  Throughput is equal to latency - 1, which we model using the
 ;; ppro_div automaton.
 (define_insn_reservation "ppro_fdiv_SF" 18
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "fdiv,fpspc"))))
 			 "decodern,p0+fdiv,fdiv*16")
 
 (define_insn_reservation "ppro_fdiv_SF_load" 19
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "fdiv,fpspc"))))
 			 "decoder0,p2+p0+fdiv,fdiv*16")
 
 (define_insn_reservation "ppro_fdiv_DF" 32
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "DF")
 					(eq_attr "type" "fdiv,fpspc"))))
 			 "decodern,p0+fdiv,fdiv*30")
 
 (define_insn_reservation "ppro_fdiv_DF_load" 33
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "DF")
 					(eq_attr "type" "fdiv,fpspc"))))
 			 "decoder0,p2+p0+fdiv,fdiv*30")
 
 (define_insn_reservation "ppro_fdiv_XF" 38
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "XF")
 					(eq_attr "type" "fdiv,fpspc"))))
 			 "decodern,p0+fdiv,fdiv*36")
 
 (define_insn_reservation "ppro_fdiv_XF_load" 39
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "XF")
 					(eq_attr "type" "fdiv,fpspc"))))
@@ -450,31 +450,31 @@
 ;; so they behave as "simple" instructions that need no special modelling.
 ;; We only have to model mmxshft and mmxmul.
 (define_insn_reservation "ppro_mmx_shft" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "mmxshft")))
 			 "decodern,p1")
 
 (define_insn_reservation "ppro_mmx_shft_load" 2
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "mmxshft")))
 			 "decoder0,p2+p1")
 
 (define_insn_reservation "ppro_mmx_mul" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "mmxmul")))
 			 "decodern,p0")
 
 (define_insn_reservation "ppro_mmx_mul_load" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "mmxmul")))
 			 "decoder0,p2+p0")
 
 (define_insn_reservation "ppro_sse_mmxcvt" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "mode" "DI")
 				   (eq_attr "type" "mmxcvt")))
 			 "decodern,p1")
@@ -482,7 +482,7 @@
 ;; FIXME: These are Pentium III only, but we cannot tell here if
 ;; we're generating code for PentiumPro/Pentium II or Pentium III
 ;; (define_insn_reservation "ppro_sse_mmxshft" 2
-;;			 (and (eq_attr "cpu" "pentiumpro,generic32")
+;;			 (and (eq_attr "cpu" "pentiumpro")
 ;;			      (and (eq_attr "mode" "DI")
 ;;				   (eq_attr "type" "mmxshft")))
 ;;			 "decodern,p0")
@@ -493,69 +493,69 @@
 
 ;; The sfence instruction.
 (define_insn_reservation "ppro_sse_sfence" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "unknown")
 				   (eq_attr "type" "sse")))
 			 "decoder0,p4+p3")
 
 ;; FIXME: This reservation is all wrong when we're scheduling sqrtss.
 (define_insn_reservation "ppro_sse_SF" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "mode" "SF")
 				   (eq_attr "type" "sse")))
 			 "decodern,p0")
 
 (define_insn_reservation "ppro_sse_add_SF" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "sseadd"))))
 			 "decodern,p1")
 
 (define_insn_reservation "ppro_sse_add_SF_load" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "sseadd"))))
 			 "decoder0,p2+p1")
 
 (define_insn_reservation "ppro_sse_cmp_SF" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "ssecmp"))))
 			 "decoder0,p1")
 
 (define_insn_reservation "ppro_sse_cmp_SF_load" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "ssecmp"))))
 			 "decoder0,p2+p1")
 
 (define_insn_reservation "ppro_sse_comi_SF" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "ssecomi"))))
 			 "decodern,p0")
 
 (define_insn_reservation "ppro_sse_comi_SF_load" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "ssecomi"))))
 			 "decoder0,p2+p0")
 
 (define_insn_reservation "ppro_sse_mul_SF" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "ssemul"))))
 			"decodern,p0")
 
 (define_insn_reservation "ppro_sse_mul_SF_load" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "ssemul"))))
@@ -563,109 +563,109 @@
 
 ;; FIXME: ssediv doesn't close p0 for 17 cycles, surely???
 (define_insn_reservation "ppro_sse_div_SF" 18
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "ssediv"))))
 			 "decoder0,p0*17")
 
 (define_insn_reservation "ppro_sse_div_SF_load" 18
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "ssediv"))))
 			 "decoder0,(p2+p0),p0*16")
 
 (define_insn_reservation "ppro_sse_icvt_SF" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "mode" "SF")
 				   (eq_attr "type" "sseicvt")))
 			 "decoder0,(p2+p1)*2")
 
 (define_insn_reservation "ppro_sse_icvt_SI" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "mode" "SI")
 				   (eq_attr "type" "sseicvt")))
 			 "decoder0,(p2+p1)")
 
 (define_insn_reservation "ppro_sse_mov_SF" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "ssemov"))))
 			 "decoder0,(p0|p1)")
 
 (define_insn_reservation "ppro_sse_mov_SF_load" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "ssemov"))))
 			 "decoder0,p2+(p0|p1)")
 
 (define_insn_reservation "ppro_sse_mov_SF_store" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "store")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "ssemov"))))
 			 "decoder0,p4+p3")
 
 (define_insn_reservation "ppro_sse_V4SF" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "mode" "V4SF")
 				   (eq_attr "type" "sse")))
 			 "decoder0,p1*2")
 
 (define_insn_reservation "ppro_sse_add_V4SF" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "sseadd"))))
 			 "decoder0,p1*2")
 
 (define_insn_reservation "ppro_sse_add_V4SF_load" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "sseadd"))))
 			 "decoder0,(p2+p1)*2")
 
 (define_insn_reservation "ppro_sse_cmp_V4SF" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "ssecmp"))))
 			 "decoder0,p1*2")
 
 (define_insn_reservation "ppro_sse_cmp_V4SF_load" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "ssecmp"))))
 			 "decoder0,(p2+p1)*2")
 
 (define_insn_reservation "ppro_sse_cvt_V4SF" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none,unknown")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "ssecvt"))))
 			 "decoder0,p1*2")
 
 (define_insn_reservation "ppro_sse_cvt_V4SF_other" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "!none,unknown")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "ssecmp"))))
 			 "decoder0,p1,p4+p3")
 
 (define_insn_reservation "ppro_sse_mul_V4SF" 5
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "ssemul"))))
 			"decoder0,p0*2")
 
 (define_insn_reservation "ppro_sse_mul_V4SF_load" 5
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "ssemul"))))
@@ -673,49 +673,49 @@
 
 ;; FIXME: p0 really closed this long???
 (define_insn_reservation "ppro_sse_div_V4SF" 48
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "ssediv"))))
 			 "decoder0,p0*34")
 
 (define_insn_reservation "ppro_sse_div_V4SF_load" 48
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "ssediv"))))
 			 "decoder0,(p2+p0)*2,p0*32")
 
 (define_insn_reservation "ppro_sse_log_V4SF" 2
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "sselog,sselog1"))))
 			 "decodern,p1")
 
 (define_insn_reservation "ppro_sse_log_V4SF_load" 2
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "sselog,sselog1"))))
 			 "decoder0,(p2+p1)")
 
 (define_insn_reservation "ppro_sse_mov_V4SF" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "ssemov"))))
 			 "decoder0,(p0|p1)*2")
 
 (define_insn_reservation "ppro_sse_mov_V4SF_load" 2
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "ssemov"))))
 			 "decoder0,p2*2")
 
 (define_insn_reservation "ppro_sse_mov_V4SF_store" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "store")
 				   (and (eq_attr "mode" "V4SF")
 					(eq_attr "type" "ssemov"))))
@@ -729,7 +729,7 @@
 ;; reg-reg instructions produce 1 uop so they can be decoded on any of
 ;; the three decoders.
 (define_insn_reservation "ppro_insn" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "none,unknown")
 				   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
 			 "decodern,(p0|p1)")
@@ -737,13 +737,13 @@
 ;; read-modify and register-memory instructions have 2 or three uops,
 ;; so they have to be decoded on decoder0.
 (define_insn_reservation "ppro_insn_load" 3
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
 			 "decoder0,p2+(p0|p1)")
 
 (define_insn_reservation "ppro_insn_store" 1
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "store")
 				   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
 			 "decoder0,(p0|p1),p4+p3")
@@ -751,7 +751,7 @@
 ;; read-modify-store instructions produce 4 uops so they have to be
 ;; decoded on decoder0 as well.
 (define_insn_reservation "ppro_insn_both" 4
-			 (and (eq_attr "cpu" "pentiumpro,generic32")
+			 (and (eq_attr "cpu" "pentiumpro")
 			      (and (eq_attr "memory" "both")
 				   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
 			 "decoder0,p2+(p0|p1),p4+p3")