diff options
| author | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2006-05-08 03:43:07 +0000 |
|---|---|---|
| committer | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2006-05-08 03:43:07 +0000 |
| commit | 106eecb313cf53d0e21a1f3eff8d24e522350620 (patch) | |
| tree | a7a03ed8ac9ba3fd89baa220716806dcfd30ccd2 /gcc/config/i386/sse.md | |
| parent | bca7f4ee6211d82492ed1baba17a580c3269c04d (diff) | |
| download | gcc-106eecb313cf53d0e21a1f3eff8d24e522350620.tar.gz | |
gcc/
2006-05-07 H.J. Lu <hongjiu.lu@intel.com>
PR target/24879
* config/i386/pmmintrin.h (_mm_monitor): Remove macro. Use
inline function.
(_mm_mwait): Likewise.
* config/i386/sse.md (sse3_mwait): Replace "mwait\t%0, %1" with
"mwait".
(sse3_monitor): Make it 32bit only.
(sse3_monitor64): New. 64bit monitor.
gcc/testsuite/
2006-05-07 H.J. Lu <hongjiu.lu@intel.com>
PR target/24879
* gcc.target/i386/monitor.c: New file.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@113617 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386/sse.md')
| -rw-r--r-- | gcc/config/i386/sse.md | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 50eced2ec32..ed36276c589 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3972,7 +3972,10 @@ (match_operand:SI 1 "register_operand" "c")] UNSPECV_MWAIT)] "TARGET_SSE3" - "mwait\t%0, %1" +;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used. +;; Since 32bit register operands are implicitly zero extended to 64bit, +;; we only need to set up 32bit registers. + "mwait" [(set_attr "length" "3")]) (define_insn "sse3_monitor" @@ -3980,6 +3983,18 @@ (match_operand:SI 1 "register_operand" "c") (match_operand:SI 2 "register_operand" "d")] UNSPECV_MONITOR)] - "TARGET_SSE3" + "TARGET_SSE3 && !TARGET_64BIT" "monitor\t%0, %1, %2" [(set_attr "length" "3")]) + +(define_insn "sse3_monitor64" + [(unspec_volatile [(match_operand:DI 0 "register_operand" "a") + (match_operand:SI 1 "register_operand" "c") + (match_operand:SI 2 "register_operand" "d")] + UNSPECV_MONITOR)] + "TARGET_SSE3 && TARGET_64BIT" +;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in +;; RCX and RDX are used. Since 32bit register operands are implicitly +;; zero extended to 64bit, we only need to set up 32bit registers. + "monitor" + [(set_attr "length" "3")]) |