2015-04-27 Ilya Tocar <ilya.tocar@intel.com>

	* config/i386/i386.h (EXT_REX_SSE_REG_P): New.
	* config/i386/i386.md (*cmpi<FPCMP:unord><MODEF:mode>_mixed): Use "v"
	constraint.
	(*movxi_internal_avx512f): Ditto.
	(define_split): Check for xmm16+, when splitting scalar float_extend.
	(*extendsfdf2_mixed): Use "v" constraint.
	(define_split): Check for xmm16+, when splitting scalar float_truncate.
	(*truncdfsf_fast_sse): Use "v" constraint.
	(fix_trunc<MODEF:mode><SWI48:mode>_sse): Ditto.
	(*float<SWI48:mode><MODEF:mode>2_sse): Ditto.
	(define_peephole2): Check for xmm16+, when converting scalar
	float_truncate.
	(define_peephole2): Check for xmm16+, when converting scalar
	float_extend.
	(*fop_<mode>_comm_mixed): Use "v" constraint.
	(*fop_<mode>_comm_sse): Ditto.
	(*fop_<mode>_1_mixed): Ditto.
	(*sqrt<mode>2_sse): Ditto.
	(*ieee_s<ieee_maxmin><mode>3): Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222470 138bc75d-0d04-0410-961f-82ee72b054a4

2 files changed, 30 insertions, 20 deletions

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index d9313305c51..a645c2a21a5 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1484,6 +1484,8 @@ enum reg_class
 #define REX_SSE_REGNO_P(N) \
   IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
 
+#define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X)))
+
 #define EXT_REX_SSE_REGNO_P(N) \
   IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 3e8474c4227..937871a5af5 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1644,8 +1644,8 @@
 (define_insn "*cmpi<FPCMP:unord><MODEF:mode>_mixed"
   [(set (reg:FPCMP FLAGS_REG)
 	(compare:FPCMP
-	  (match_operand:MODEF 0 "register_operand" "f,x")
-	  (match_operand:MODEF 1 "nonimmediate_operand" "f,xm")))]
+	  (match_operand:MODEF 0 "register_operand" "f,v")
+	  (match_operand:MODEF 1 "nonimmediate_operand" "f,vm")))]
   "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
   "* return output_fp_compare (insn, operands, true,
 			       <FPCMP:MODE>mode == CCFPUmode);"
@@ -1944,8 +1944,8 @@
    (set_attr "length_immediate" "1")])
 
 (define_insn "*movxi_internal_avx512f"
-  [(set (match_operand:XI 0 "nonimmediate_operand" "=x,x ,m")
-	(match_operand:XI 1 "vector_move_operand"  "C ,xm,x"))]
+  [(set (match_operand:XI 0 "nonimmediate_operand" "=v,v ,m")
+	(match_operand:XI 1 "vector_move_operand"  "C ,vm,v"))]
   "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
 {
   switch (which_alternative)
@@ -3988,7 +3988,9 @@
 	  (match_operand:SF 1 "nonimmediate_operand")))]
   "TARGET_USE_VECTOR_FP_CONVERTS
    && optimize_insn_for_speed_p ()
-   && reload_completed && SSE_REG_P (operands[0])"
+   && reload_completed && SSE_REG_P (operands[0])
+   && (!EXT_REX_SSE_REG_P (operands[0])
+       || TARGET_AVX512VL)"
    [(set (match_dup 2)
 	 (float_extend:V2DF
 	   (vec_select:V2SF
@@ -4033,9 +4035,9 @@
   "operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));")
 
 (define_insn "*extendsfdf2_mixed"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,x")
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,v")
         (float_extend:DF
-	  (match_operand:SF 1 "nonimmediate_operand" "fm,f,xm")))]
+	  (match_operand:SF 1 "nonimmediate_operand" "fm,f,vm")))]
   "TARGET_SSE2 && TARGET_SSE_MATH"
 {
   switch (which_alternative)
@@ -4136,7 +4138,9 @@
 	  (match_operand:DF 1 "nonimmediate_operand")))]
   "TARGET_USE_VECTOR_FP_CONVERTS
    && optimize_insn_for_speed_p ()
-   && reload_completed && SSE_REG_P (operands[0])"
+   && reload_completed && SSE_REG_P (operands[0])
+   && (!EXT_REX_SSE_REG_P (operands[0])
+       || TARGET_AVX512VL)"
    [(set (match_dup 2)
 	 (vec_concat:V4SF
 	   (float_truncate:V2SF
@@ -4189,9 +4193,9 @@
 ;; SSE alternative doesn't depend on flag_unsafe_math_optimizations,
 ;; because nothing we do there is unsafe.
 (define_insn "*truncdfsf_fast_mixed"
-  [(set (match_operand:SF 0 "nonimmediate_operand"   "=fm,x")
+  [(set (match_operand:SF 0 "nonimmediate_operand"   "=fm,v")
         (float_truncate:SF
-          (match_operand:DF 1 "nonimmediate_operand" "f  ,xm")))]
+          (match_operand:DF 1 "nonimmediate_operand" "f  ,vm")))]
   "TARGET_SSE2 && TARGET_SSE_MATH"
 {
   switch (which_alternative)
@@ -4521,7 +4525,7 @@
 ;; When SSE is available, it is always faster to use it!
 (define_insn "fix_trunc<MODEF:mode><SWI48:mode>_sse"
   [(set (match_operand:SWI48 0 "register_operand" "=r,r")
-	(fix:SWI48 (match_operand:MODEF 1 "nonimmediate_operand" "x,m")))]
+	(fix:SWI48 (match_operand:MODEF 1 "nonimmediate_operand" "v,m")))]
   "SSE_FLOAT_MODE_P (<MODEF:MODE>mode)
    && (!TARGET_FISTTP || TARGET_SSE_MATH)"
   "%vcvtt<MODEF:ssemodesuffix>2si<SWI48:rex64suffix>\t{%1, %0|%0, %1}"
@@ -4841,7 +4845,7 @@
 })
 
 (define_insn "*float<SWI48:mode><MODEF:mode>2_mixed"
-  [(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
+  [(set (match_operand:MODEF 0 "register_operand" "=f,v,v")
 	(float:MODEF
 	  (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
   "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
@@ -4944,7 +4948,9 @@
    && optimize_function_for_speed_p (cfun)
    && SSE_REG_P (operands[0])
    && (!SSE_REG_P (operands[1])
-       || REGNO (operands[0]) != REGNO (operands[1]))"
+       || REGNO (operands[0]) != REGNO (operands[1]))
+   && (!EXT_REX_SSE_REG_P (operands[0])
+       || TARGET_AVX512VL)"
   [(set (match_dup 0)
 	(vec_merge:V4SF
 	  (vec_duplicate:V4SF
@@ -4971,7 +4977,9 @@
    && optimize_function_for_speed_p (cfun)
    && SSE_REG_P (operands[0])
    && (!SSE_REG_P (operands[1])
-       || REGNO (operands[0]) != REGNO (operands[1]))"
+       || REGNO (operands[0]) != REGNO (operands[1]))
+   && (!EXT_REX_SSE_REG_P (operands[0])
+       || TARGET_AVX512VL)"
   [(set (match_dup 0)
         (vec_merge:V2DF
           (float_extend:V2DF
@@ -13955,9 +13963,9 @@
 })
 
 (define_insn "*sqrt<mode>2_sse"
-  [(set (match_operand:MODEF 0 "register_operand" "=x")
+  [(set (match_operand:MODEF 0 "register_operand" "=v")
 	(sqrt:MODEF
-	  (match_operand:MODEF 1 "nonimmediate_operand" "xm")))]
+	  (match_operand:MODEF 1 "nonimmediate_operand" "vm")))]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
   "%vsqrt<ssemodesuffix>\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "sse")
@@ -16919,17 +16927,17 @@
 	 (UNSPEC_IEEE_MIN "min")])
 
 (define_insn "*ieee_s<ieee_maxmin><mode>3"
-  [(set (match_operand:MODEF 0 "register_operand" "=x,x")
+  [(set (match_operand:MODEF 0 "register_operand" "=x,v")
 	(unspec:MODEF
-	  [(match_operand:MODEF 1 "register_operand" "0,x")
-	   (match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]
+	  [(match_operand:MODEF 1 "register_operand" "0,v")
+	   (match_operand:MODEF 2 "nonimmediate_operand" "xm,vm")]
 	  IEEE_MAXMIN))]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
   "@
    <ieee_maxmin><ssemodesuffix>\t{%2, %0|%0, %2}
    v<ieee_maxmin><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,avx")
-   (set_attr "prefix" "orig,vex")
+   (set_attr "prefix" "orig,maybe_evex")
    (set_attr "type" "sseadd")
    (set_attr "mode" "<MODE>")])