* config/alpha/alpha.md, config/arm/arm.c, config/arm/arm.h,

	config/d30v/d30v.h, config/fr30/fr30.c, config/i370/x-oe,
	config/i386/i386.c, config/i386/i386-interix.h,
	config/i386/i386.md, config/i386/i386.h, config/i386/sco5.h,
	config/i860/i860.h, config/i860/i860.md, config/m68k/aux-exit.c,
	config/m68k/m68k.c, config/mcore/mcore.c, config/mips/mips.md,
	config/ns32k/ns32k.h, config/pa/pa.c, config/rs6000/rs6000.c,
	config/sparc/sparc.c, config/m68hc11/m68hc11.c,
	config/cris/cris.c, config/cris/cris.h, config/s390/s390.c,
	config/s390/s390.h, config/stormy16/stormy16.h, doc/tm.texi: Fix
	spelling errors.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@46582 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 9 insertions, 9 deletions

diff --git a/gcc/config/i386/i386-interix.h b/gcc/config/i386/i386-interix.h
index 3da08078141..0325b68e846 100644
--- a/gcc/config/i386/i386-interix.h
+++ b/gcc/config/i386/i386-interix.h
@@ -39,7 +39,7 @@ Boston, MA 02111-1307, USA.  */
 
 /* By default, target has a 80387, uses IEEE compatible arithmetic,
    and returns float values in the 387 and needs stack probes
-   We also align doubles to 64-bits for MSVC default compatability */
+   We also align doubles to 64-bits for MSVC default compatibility */
 #undef TARGET_SUBTARGET_DEFAULT
 #define TARGET_SUBTARGET_DEFAULT \
    (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_STACK_PROBE | \
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 52e24146cb8..79aceb6c99f 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1418,7 +1418,7 @@ init_cumulative_args (cum, fntype, libname)
 }
 
 /* x86-64 register passing impleemntation.  See x86-64 ABI for details.  Goal
-   of this code is to classify each 8bytes of incomming argument by the register
+   of this code is to classify each 8bytes of incoming argument by the register
    class and assign registers accordingly.  */
 
 /* Return the union class of CLASS1 and CLASS2.
@@ -3801,7 +3801,7 @@ ix86_compute_frame_layout (frame)
 
   /* Do some sanity checking of stack_alignment_needed and
      preferred_alignment, since i386 port is the only using those features
-     that may break easilly.  */
+     that may break easily.  */
 
   if (size && !stack_alignment_needed)
     abort ();
@@ -4696,7 +4696,7 @@ legitimate_address_p (mode, addr, strict)
 
 	     This code is nonsensical, but results in addressing
 	     GOT table with pic_offset_table_rtx base.  We can't
-	     just refuse it easilly, since it gets matched by
+	     just refuse it easily, since it gets matched by
 	     "addsi3" pattern, that later gets split to lea in the
 	     case output register differs from input.  While this
 	     can be handled by separate addsi pattern for this case
@@ -12133,7 +12133,7 @@ ix86_expand_builtin (exp, target, subtarget, mode, ignore)
 }
 
 /* Store OPERAND to the memory after reload is completed.  This means
-   that we can't easilly use assign_stack_local.  */
+   that we can't easily use assign_stack_local.  */
 rtx
 ix86_force_to_memory (mode, operand)
      enum machine_mode mode;
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index f3e855cb140..85e1c35601d 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2394,7 +2394,7 @@ while (0)
    stored in a register.  This macro is only called when TYPE is a
    scalar type.
 
-   On i386 it is sometimes usefull to promote HImode and QImode
+   On i386 it is sometimes useful to promote HImode and QImode
    quantities to SImode.  The choice depends on target type.  */
 
 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) 		\
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a8a01b4874a..7c122698a5d 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -993,7 +993,7 @@
        (eq_attr "athlon_fpunits" "store"))
   1 1)
 
-;; We don't need to model the Adress Generation Unit, since we don't model
+;; We don't need to model the Address Generation Unit, since we don't model
 ;; the re-order buffer yet and thus we never schedule more than three operations
 ;; at time.  Later we may want to experiment with MD_SCHED macros modeling the
 ;; decoders independently on the functional units.
diff --git a/gcc/config/i386/sco5.h b/gcc/config/i386/sco5.h
index ca7d6c8b88d..cdc811bbc92 100644
--- a/gcc/config/i386/sco5.h
+++ b/gcc/config/i386/sco5.h
@@ -102,7 +102,7 @@ Boston, MA 02111-1307, USA.  */
 
 #undef INIT_SECTION_ASM_OP
 #define INIT_SECTION_ASM_OP_ELF		"\t.section\t.init"
-/* Rename these for COFF becuase crt1.o will try to run them. */
+/* Rename these for COFF because crt1.o will try to run them. */
 #define INIT_SECTION_ASM_OP_COFF	"\t.section\t.ctor ,\"x\""
 #define INIT_SECTION_ASM_OP	\
   ((TARGET_ELF) ? INIT_SECTION_ASM_OP_ELF : INIT_SECTION_ASM_OP_COFF)
@@ -658,7 +658,7 @@ init_section ()								\
 
 #if USE_GAS
   /* Leave ASM_SPEC undefined so we pick up the master copy from gcc.c 
-   * Undef MD_EXEC_PREFIX becuase we don't know where GAS is, but it's not
+   * Undef MD_EXEC_PREFIX because we don't know where GAS is, but it's not
    * likely in /usr/ccs/bin/ 
    */
 #undef MD_EXEC_PREFIX