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| author | kyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-08-28 06:28:56 +0000 |
|---|---|---|
| committer | kyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-08-28 06:28:56 +0000 |
| commit | 9bb6f354f0dd9a825ca08cf9203a5fc1d232fcbd (patch) | |
| tree | 43b858ee7a12bbfcbe18dd89d0c1e2db2e214426 /gcc/config/i386 | |
| parent | 5407d66281a35f7c26fb724e733feb15d4ab076a (diff) | |
| download | gcc-9bb6f354f0dd9a825ca08cf9203a5fc1d232fcbd.tar.gz | |
AVX-512. Add vcvtps2[u]qq patterns.
gcc/
* config/i386/sse.md
(define_mode_iterator VI8_256_512): New.
(define_insn "<mask_codefor>avx512dq_cvtps2qq<mode><mask_name><round_name>"):
Ditto.
(define_insn "<mask_codefor>avx512dq_cvtps2qqv2di<mask_name>"): Ditto.
(define_insn "<mask_codefor>avx512dq_cvtps2uqq<mode><mask_name><round_name>"):
Ditto.
(define_insn "<mask_codefor>avx512dq_cvtps2uqqv2di<mask_name>"): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@214668 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386')
| -rw-r--r-- | gcc/config/i386/sse.md | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c0a79dfc235..5904450d453 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -278,6 +278,9 @@ (define_mode_iterator VI8_AVX512VL [V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) +(define_mode_iterator VI8_256_512 + [V8DI (V4DI "TARGET_AVX512VL")]) + (define_mode_iterator VI1_AVX2 [(V32QI "TARGET_AVX2") V16QI]) @@ -3911,6 +3914,52 @@ (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) +(define_insn "<mask_codefor>avx512dq_cvtps2qq<mode><mask_name><round_name>" + [(set (match_operand:VI8_256_512 0 "register_operand" "=v") + (unspec:VI8_256_512 [(match_operand:<ssePSmode2> 1 "nonimmediate_operand" "<round_constraint>")] + UNSPEC_FIX_NOTRUNC))] + "TARGET_AVX512DQ && <round_mode512bit_condition>" + "vcvtps2qq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn "<mask_codefor>avx512dq_cvtps2qqv2di<mask_name>" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI + [(vec_select:V2SF + (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (parallel [(const_int 0) (const_int 1)]))] + UNSPEC_FIX_NOTRUNC))] + "TARGET_AVX512DQ && TARGET_AVX512VL" + "vcvtps2qq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "TI")]) + +(define_insn "<mask_codefor>avx512dq_cvtps2uqq<mode><mask_name><round_name>" + [(set (match_operand:VI8_256_512 0 "register_operand" "=v") + (unspec:VI8_256_512 [(match_operand:<ssePSmode2> 1 "nonimmediate_operand" "<round_constraint>")] + UNSPEC_UNSIGNED_FIX_NOTRUNC))] + "TARGET_AVX512DQ && <round_mode512bit_condition>" + "vcvtps2uqq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn "<mask_codefor>avx512dq_cvtps2uqqv2di<mask_name>" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI + [(vec_select:V2SF + (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (parallel [(const_int 0) (const_int 1)]))] + UNSPEC_UNSIGNED_FIX_NOTRUNC))] + "TARGET_AVX512DQ && TARGET_AVX512VL" + "vcvtps2uqq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "TI")]) + (define_insn "<fixsuffix>fix_truncv16sfv16si2<mask_name><round_saeonly_name>" [(set (match_operand:V16SI 0 "register_operand" "=v") (any_fix:V16SI |