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| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-07-11 18:42:44 +0000 |
|---|---|---|
| committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-07-11 18:42:44 +0000 |
| commit | bdbf1fdfb935e0271f4a0f9a8c8b5a292570ad1d (patch) | |
| tree | 47aba321f39bbf74a4d3c3b2b1e52a00eb43be67 /gcc/config/i386 | |
| parent | decb541dcb9a0aa08ee26a6257688391220adfef (diff) | |
| download | gcc-bdbf1fdfb935e0271f4a0f9a8c8b5a292570ad1d.tar.gz | |
PR target/32661
* config/i386/sse.md (*sse2_storeq_rex64): Handle 64bit mem->reg moves.
(*vec_extractv2di_1_sse2): Disable for TARGET_64BIT.
(*vec_extractv2di_1_rex64): New insn pattern.
testsuite/ChangeLog:
PR target/32661
* gcc.target/i386/pr32661-1.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@126557 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386')
| -rw-r--r-- | gcc/config/i386/sse.md | 31 |
1 files changed, 26 insertions, 5 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 027d43bfb6c..3164077862a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4587,12 +4587,17 @@ "") (define_insn "*sse2_storeq_rex64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=mx,r") + [(set (match_operand:DI 0 "nonimmediate_operand" "=mx,r,r") (vec_select:DI - (match_operand:V2DI 1 "register_operand" "x,Yi") + (match_operand:V2DI 1 "nonimmediate_operand" "x,Yi,o") (parallel [(const_int 0)])))] - "TARGET_64BIT && TARGET_SSE" - "#") + "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "@ + # + # + mov{q}\t{%1, %0|%0, %1}" + [(set_attr "type" "*,*,imov") + (set_attr "mode" "*,*,DI")]) (define_insn "*sse2_storeq" [(set (match_operand:DI 0 "nonimmediate_operand" "=mx") @@ -4617,12 +4622,28 @@ operands[1] = gen_rtx_REG (DImode, REGNO (operands[1])); }) +(define_insn "*vec_extractv2di_1_rex64" + [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r") + (vec_select:DI + (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o,o") + (parallel [(const_int 1)])))] + "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "@ + movhps\t{%1, %0|%0, %1} + psrldq\t{$8, %0|%0, 8} + movq\t{%H1, %0|%0, %H1} + mov{q}\t{%H1, %0|%0, %H1}" + [(set_attr "type" "ssemov,sseishft,ssemov,imov") + (set_attr "memory" "*,none,*,*") + (set_attr "mode" "V2SF,TI,TI,DI")]) + (define_insn "*vec_extractv2di_1_sse2" [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x") (vec_select:DI (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o") (parallel [(const_int 1)])))] - "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "!TARGET_64BIT + && TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ movhps\t{%1, %0|%0, %1} psrldq\t{$8, %0|%0, 8} |