* config/ia64/crti.asm: Clean up trailing whitespace.

        Remove trailing hashes (#) from identifiers.

        * config/ia64/crtn.asm: Ditto.

        * config/ia64/crtend.asm: Remove trailing hashes (#) from
        identifiers.
        (__do_global_ctors_aux): Align to 32-byte boundary.  Add unwind
        directives.  Drop explicit bundling---it just makes the code
        harder to read.  Don't save/restore gp needlessly.

        * config/ia64/crtbegin.asm: Remove trailing hashes (#) from
        identifiers (they're only needed if the identifier would clash
        with a register name otherwise).
        (__do_global_dtors_aux): Align to 32-byte boundary. Add unwind
        directives.  Drop explicit bundling---it just makes the code
        harder to read.
        (__do_jv_register_classes): Ditto.
        (.fini_array): Remove "progbits" (newer
        assemblers don't like wrong section-types).
        (.init_array): Ditto.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@65150 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 124 insertions, 136 deletions

diff --git a/gcc/config/ia64/crtbegin.asm b/gcc/config/ia64/crtbegin.asm
index cb49e10bc56..c64de028eef 100644
--- a/gcc/config/ia64/crtbegin.asm
+++ b/gcc/config/ia64/crtbegin.asm
@@ -33,33 +33,33 @@ __DTOR_LIST__:
 __JCR_LIST__:
 
 .section .sdata
-	.type dtor_ptr#,@object
-	.size dtor_ptr#,8
+	.type dtor_ptr,@object
+	.size dtor_ptr,8
 dtor_ptr:
-	data8	@gprel(__DTOR_LIST__# + 8)
+	data8	@gprel(__DTOR_LIST__ + 8)
 
 	/* A handle for __cxa_finalize to manage c++ local destructors.  */
-	.global __dso_handle#
-	.type __dso_handle#,@object
-	.size __dso_handle#,8
+	.global __dso_handle
+	.type __dso_handle,@object
+	.size __dso_handle,8
 #ifdef SHARED
 	.section .data
 __dso_handle:
-	data8	__dso_handle#
+	data8	__dso_handle
 #else
 	.section .bss
 __dso_handle:
 	data8	0
 #endif
-	.hidden __dso_handle#
+	.hidden __dso_handle
 
 
 #ifdef HAVE_INITFINI_ARRAY
 
-.section .fini_array,"a","progbits"
+.section .fini_array,"a"
 	data8 @fptr(__do_global_dtors_aux)
 
-.section .init_array,"a","progbits"
+.section .init_array,"a"
 	data8 @fptr(__do_jv_register_classes)
 	data8 @fptr(__do_global_ctors_aux)
 
@@ -79,7 +79,7 @@ __dso_handle:
  */
 .section .fini,"ax","progbits"
 	{ .mlx
-	  movl r2 = @pcrel(__do_global_dtors_aux# - 16)
+	  movl r2 = @pcrel(__do_global_dtors_aux - 16)
 	}
 	{ .mii
 	  mov r3 = ip
@@ -97,7 +97,7 @@ __dso_handle:
 
 .section .init,"ax","progbits"
 	{ .mlx
-	  movl r2 = @pcrel(__do_jv_register_classes# - 16)
+	  movl r2 = @pcrel(__do_jv_register_classes - 16)
 	}
 	{ .mii
 	  mov r3 = ip
@@ -113,56 +113,58 @@ __dso_handle:
 #endif /* !HAVE_INITFINI_ARRAY */
 
 .section .text
-	.align	16
-	.proc	__do_global_dtors_aux#
+	.align	32
+	.proc	__do_global_dtors_aux
 __do_global_dtors_aux:
+	.prologue
 #ifndef SHARED
-	{ .mii
-	  alloc loc3 = ar.pfs, 0, 4, 1, 0
-	  addl loc0 = @gprel(dtor_ptr#), gp
-	  mov loc1 = b0
-	}
-	{ .mib
-	  mov loc2 = gp
-	  br.sptk.few 1f
-	  ;;
-	}
+	.save ar.pfs, r35
+	alloc loc3 = ar.pfs, 0, 4, 1, 0
+	addl loc0 = @gprel(dtor_ptr), gp
+	.save rp, loc1
+	mov loc1 = rp
+	.body
+
+	mov loc2 = gp
+	nop 0
+	br.sptk.many 1f
+	;;
 #else
 	/*
 		if (__cxa_finalize)
 		  __cxa_finalize(__dso_handle)
 	*/
-	{ .mii
-	  alloc loc3 = ar.pfs, 0, 4, 1, 0
-	  addl loc0 = @gprel(dtor_ptr#), gp
-	  addl r16 = @ltoff(@fptr(__cxa_finalize#)), gp
-	  ;;
-	}
-	{ .mmi
-	  ld8 r16 = [r16]
-	  ;;
-	  addl out0 = @ltoff(__dso_handle#), gp
-	  cmp.ne p7, p0 = r0, r16
-	  ;;
-	}
-	{ .mmi
-	  ld8 out0 = [out0]
-(p7)	  ld8 r18 = [r16], 8
-	  mov loc1 = b0
-	  ;;
-	}
-	{ .mfi
-	  mov loc2 = gp
-(p7)	  mov b6 = r18
-	}
-	{
-	  .mfb
-(p7)	  ld8 gp = [r16]
-(p7)	  br.call.sptk.many b0 = b6
-	}
-	{ .mfb
-	  br.sptk.few 1f
-	}
+	.save ar.pfs, r35
+	alloc loc3 = ar.pfs, 0, 4, 1, 0
+	addl loc0 = @gprel(dtor_ptr), gp
+	addl r16 = @ltoff(@fptr(__cxa_finalize)), gp
+	;;
+
+	ld8 r16 = [r16]
+	;;
+	addl out0 = @ltoff(__dso_handle), gp
+	cmp.ne p7, p0 = r0, r16
+	;;
+
+	ld8 out0 = [out0]
+(p7)	ld8 r18 = [r16], 8
+	.save rp, loc1
+	mov loc1 = rp
+	.body
+	;;
+
+	mov loc2 = gp
+(p7)	ld8 gp = [r16]
+(p7)	mov b6 = r18
+
+	nop 0
+	nop 0
+(p7)	br.call.sptk.many rp = b6
+	;;
+
+	nop 0
+	nop 0
+	br.sptk.many 1f
 #endif
 	/*
 		do {
@@ -171,89 +173,75 @@ __do_global_dtors_aux:
 		} while (dtor_ptr);
 	*/
 0:
-	{ .mmi
-	  st8 [loc0] = r15
-	  ld8 r17 = [r16], 8
-	  ;;
-	}
-	{ .mib
-	  ld8 gp = [r16]
-	  mov b6 = r17
-	  br.call.sptk.many b0 = b6
-	}
-1:
-	{ .mmi
-	  ld8 r15 = [loc0]
-	  ;;
-	  add r16 = r15, loc2
-	  adds r15 = 8, r15
-	  ;;
-	}
-	{ .mmi
-	  ld8 r16 = [r16]
-	  mov gp = loc2
-	  mov b0 = loc1
-	  ;;
-	}
-	{ .mib
-	  cmp.ne p6, p0 = r0, r16
-	  mov ar.pfs = loc3
-(p6)	  br.cond.sptk.few 0b
-	}
-	{ .bbb
-	  br.ret.sptk.many b0
-	  ;;
-	}
-	.endp	__do_global_dtors_aux#
-
-	.align	16
-	.proc	__do_jv_register_classes#
+	st8 [loc0] = r15		// update dtor_ptr (in memory)
+	ld8 r17 = [r16], 8		// r17 <- dtor's entry-point
+	nop 0
+	;;
+
+	ld8 gp = [r16]			// gp <- dtor's gp
+	mov b6 = r17
+	br.call.sptk.many rp = b6
+
+1:	ld8 r15 = [loc0]		// r15 <- dtor_ptr (gp-relative)
+	;;
+	add r16 = r15, loc2		// r16 <- dtor_ptr (absolute)
+	adds r15 = 8, r15
+	;;
+
+	ld8 r16 = [r16]			// r16 <- pointer to dtor's fdesc
+	mov rp = loc1
+	mov ar.pfs = loc3
+	;;
+
+	cmp.ne p6, p0 = r0, r16
+(p6)	br.cond.sptk.few 0b
+	br.ret.sptk.many rp
+	.endp __do_global_dtors_aux
+
+	.align	32
+	.proc	__do_jv_register_classes
 __do_jv_register_classes:
-	{ .mlx
-	  alloc loc2 = ar.pfs, 0, 3, 1, 0
-	  movl out0 = @gprel(__JCR_LIST__)
-	  ;;
-	}
-	{ .mmi
-	  addl r14 = @ltoff(@fptr(_Jv_RegisterClasses)), gp
-	  add out0 = out0, gp
-	  ;;
-	}
-	{ .mmi
-	  ld8 r14 = [r14]
-	  ld8 r15 = [out0]
-	  cmp.ne p6, p0 = r0, r0
-	  ;;
-	}
-	{ .mib
-	  cmp.eq.or p6, p0 = r0, r14
-	  cmp.eq.or p6, p0 = r0, r15
-(p6)	  br.ret.sptk.many b0
-	}
-	{ .mii
-	  ld8 r15 = [r14], 8
-	  mov loc0 = b0
-	  mov loc1 = gp
-	  ;;
-	}
-	{ .mib
-	  ld8 gp = [r14]
-	  mov b6 = r15
-	  br.call.sptk.many b0 = b6
-	  ;;
-	}
-	{ .mii
-	  mov gp = loc1
-	  mov b0 = loc0
-	  mov ar.pfs = loc2
-	}
-	{ .bbb
-	  br.ret.sptk.many b0
-	  ;;
-	}
-	.endp	__do_jv_register_classes#
+	.save ar.pfs, r33
+	alloc loc1 = ar.pfs, 0, 2, 1, 0
+	movl out0 = @gprel(__JCR_LIST__)
+	;;
+
+	addl r14 = @ltoff(@fptr(_Jv_RegisterClasses)), gp
+	add out0 = out0, gp
+	.save rp, loc0
+	mov loc0 = rp
+	.body
+	;;
+
+	ld8 r14 = [r14]
+	ld8 r15 = [out0]
+	cmp.ne p6, p0 = r0, r0
+	;;
+
+	cmp.eq.or p6, p0 = r0, r14
+	cmp.eq.or p6, p0 = r0, r15
+(p6)	br.ret.sptk.many rp
+
+	ld8 r15 = [r14], 8
+	;;
+	ld8 gp = [r14]
+	mov b6 = r15
+
+	nop 0
+	nop 0
+	br.call.sptk.many rp = b6
+	;;
+
+	nop 0
+	mov rp = loc0
+	mov ar.pfs = loc1
+
+	nop 0
+	nop 0
+	br.ret.sptk.many rp
+	.endp	__do_jv_register_classes
 
 #ifdef SHARED
-.weak __cxa_finalize#
+.weak __cxa_finalize
 #endif
 .weak _Jv_RegisterClasses