diff options
| author | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2001-08-19 03:04:19 +0000 |
|---|---|---|
| committer | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2001-08-19 03:04:19 +0000 |
| commit | 34a64f802f12f6d4df7e7dddfdda1a80d7601d92 (patch) | |
| tree | f05313d8fdbcc9289591f51b7bf29335cf3310d0 /gcc/config/ia64/ia64.h | |
| parent | ec10232181a9e553fe74cfbb760717dc6155e628 (diff) | |
| download | gcc-34a64f802f12f6d4df7e7dddfdda1a80d7601d92.tar.gz | |
* flow.c (mark_regs_live_at_end): Use regs_invalidated_by_call.
* regclass.c (init_reg_sets_1): Fix typo.
* config/ia64/ia64.c (ar_pfs_reg_operand): New.
(ia64_expand_call): Pass ar.pfs to sibcall expanders.
(ia64_compute_frame_size): Make ar.unat live when in use.
(ia64_epilogue_uses): Reformat; do not check current_function_is_leaf
for ar.pfs; remove ar.unat handling.
* config/ia64/ia64.h (CALL_REALLY_USED_REGISTERS): ar.unat is
call-saved.
(PREDICATE_CODES): Add ar_pfs_reg_operand.
* config/ia64/ia64-protos.h: Update decls.
* config/ia64/ia64.md (sibcall_nopic): Use ar.pfs.
(sibcall_pic): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@45021 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/ia64/ia64.h')
| -rw-r--r-- | gcc/config/ia64/ia64.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index d1a1feded61..97e609fd21e 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -635,11 +635,11 @@ while (0) /* Like `CALL_USED_REGISTERS' but used to overcome a historical problem which makes CALL_USED_REGISTERS *always* include - all the FIXED_REGISTERS. Until this problem has been + all the FIXED_REGISTERS. Until this problem has been resolved this macro can be used to overcome this situation. In particular, block_propagate() requires this list be acurate, or we can remove registers which should be live. - This macro is used in regs_invalidated_by_call ()*/ + This macro is used in regs_invalidated_by_call. */ #define CALL_REALLY_USED_REGISTERS \ { /* General registers. */ \ @@ -668,7 +668,7 @@ while (0) /* Branch registers. */ \ 1, 0, 0, 0, 0, 0, 1, 1, \ /*FP RA CCV UNAT PFS LC EC */ \ - 0, 0, 1, 1, 1, 0, 0 \ + 0, 0, 1, 0, 1, 0, 0 \ } @@ -2667,6 +2667,7 @@ do { \ { "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \ { "ar_lc_reg_operand", {REG}}, \ { "ar_ccv_reg_operand", {REG}}, \ +{ "ar_pfs_reg_operand", {REG}}, \ { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ { "destination_tfmode_operand", {SUBREG, REG, MEM}}, \ { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, |