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| author | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2000-08-20 19:03:03 +0000 |
|---|---|---|
| committer | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2000-08-20 19:03:03 +0000 |
| commit | 2f3e8f0e6f92918408e3580ada484ea5fac22a06 (patch) | |
| tree | f96e69f7cf9fd58c5cd74ec965b6c8f8d57055d7 /gcc/config/ia64/ia64.md | |
| parent | 547ac4b1568c4f7286e5ce5a1e6bd5a9a8c7a528 (diff) | |
| download | gcc-2f3e8f0e6f92918408e3580ada484ea5fac22a06.tar.gz | |
* config/ia64/ia64.c (emit_insn_group_barriers): Stop if ar.lc
assigned before a loop.
* config/ia64/ia64.md (ashlsi3): Zero extend the shift count.
(ashrsi3, lshrsi3): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@35823 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/ia64/ia64.md')
| -rw-r--r-- | gcc/config/ia64/ia64.md | 31 |
1 files changed, 25 insertions, 6 deletions
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index e0173e6a344..3afddeac929 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -2012,10 +2012,27 @@ ;; :: ;; :::::::::::::::::::: -(define_insn "ashlsi3" +(define_expand "ashlsi3" + [(set (match_operand:SI 0 "register_operand" "") + (ashift:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "reg_or_5bit_operand" "")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + { + /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now + we've got to get rid of stray bits outside the SImode register. */ + rtx subshift = gen_reg_rtx (DImode); + emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); + operands[2] = subshift; + } +}") + +(define_insn "*ashlsi3_internal" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (ashift:SI (match_operand:SI 1 "register_operand" "r,r,r") - (match_operand:SI 2 "reg_or_5bit_operand" "R,n,r")))] + (match_operand:DI 2 "reg_or_5bit_operand" "R,n,r")))] "" "@ shladd %0 = %1, %2, r0 @@ -2036,9 +2053,10 @@ GEN_INT (32 - INTVAL (operands[2])), operands[2])); else { + rtx subshift = gen_reg_rtx (DImode); emit_insn (gen_extendsidi2 (subtarget, operands[1])); - emit_insn (gen_ashrdi3 (subtarget, subtarget, - gen_lowpart (DImode, operands[2]))); + emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); + emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); } emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); DONE; @@ -2057,9 +2075,10 @@ GEN_INT (32 - INTVAL (operands[2])), operands[2])); else { + rtx subshift = gen_reg_rtx (DImode); emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); - emit_insn (gen_lshrdi3 (subtarget, subtarget, - gen_lowpart (DImode, operands[2]))); + emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); + emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); } emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); DONE; |