* config/ia64/ia64-protos.h: Update.

	* config/ia64/ia64.c (signed_inequality_operator): New.
	(ia64_expand_compare): New.
	(ia64_register_move_cost): Handle PR_REGS moves.
	(ia64_secondary_reload_class): Require a GR when moving to a PR.
	(struct reg_write_state): Add written_by_and/or.
	(struct reg_flags): Add is_and/or.
	(rws_update): Set them.
	(rws_access_regno): Test them to allow parallel comparisons.
	(rtx_needs_barrier): Recognize parallel comparisons.
	(emit_insn_group_barriers): Set prev_insn after a call stop bit.
	Call recog_memoized; ignore pred_rel_mutex.
	(emit_predicate_relation_info): Don't call find_basic_blocks here.
	(ia64_reorg): Do it here instead.
	* config/ia64/ia64.h: s/CCmode/BImode/g
	(MODES_TIEABLE_P): Don't tie BImode.
	(PREFERRED_RELOAD_CLASS): Do not reload operations into AR regs.
	(CONST_COSTS): Pick sensible values for CONST_INT based on context.
	(RTX_COSTS): Make multiply 4 insns.
	(MEMORY_MOVE_COST): New.
	(PREDICATE_CODES): Update.
	* config/ia64/ia64.md: s/CCmode/BImode/g
	(movcci, movbi): New.
	(andbi3, andcmbi3, iorbi3, iorcmbi3, one_cmplbi2): New.
	(cmpsi_and_0, cmpsi_and_1, cmpsi_andnot_0, cmpsi_andnot_1): New.
	(cmpdi_and_0, cmpdi_and_1, cmpdi_andnot_0, cmpdi_andnot_1): New.
	(tbit_and_0, tbit_and_1, tbit_and_2, tbit_and_3): New.
	(cmpsi_or_0, cmpsi_or_1, cmpsi_orcm_0, cmpsi_orcm_1): New.
	(cmpdi_or_0, cmpdi_or_1, cmpdi_orcm_0, cmpdi_orcm_1): New.
	(tbit_or_0, tbit_or_1, tbit_or_2, tbit_or_3): New.
	(mulsi, muldi): Use xmpy not xma.
	(cmpbi): New.
	(movcc, movcc_internal): Remove.
	(branch expanders): Use ia64_expand_compare.
	(setcc expanders): Likewise.
	(cmov insns): Use move_operand and ia64_move_ok.
	(pred_rel_mutex): Use unspec not unspec_volatile.  Prevent the
	scheduler from moving it past a use.
	* config/ia64/build.hacks: Remove.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@36510 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 799 insertions, 489 deletions

diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 704959222d2..45479a22c77 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -60,6 +60,7 @@
 ;;	3	fr_spill
 ;;	4	fr_restore
 ;;	5	recip_approx
+;;	7	pred_rel_mutex
 ;;	8	popcnt
 ;;	12	mf
 ;;	13	cmpxchg_acq
@@ -72,7 +73,6 @@
 ;;	1	blockage
 ;;	2	insn_group_barrier
 ;;	5	set_bsp
-;;	7	pred.rel.mutex
 ;;	8	pred.safe_across_calls all
 ;;	9	pred.safe_across_calls normal
 
@@ -159,6 +159,61 @@
 ;; ::
 ;; ::::::::::::::::::::
 
+;; Set of a single predicate register.  This is only used to implement
+;; pr-to-pr move and complement.
+
+(define_insn "*movcci"
+  [(set (match_operand:CCI 0 "register_operand" "=c,c,c")
+	(match_operand:CCI 1 "nonmemory_operand" "O,n,c"))]
+  ""
+  "@
+   cmp.ne %0, p0 = r0, r0
+   cmp.eq %0, p0 = r0, r0
+   (%1) cmp.eq.unc %0, p0 = r0, r0"
+  [(set_attr "type" "A")
+   (set_attr "predicable" "no")])
+
+(define_insn "movbi"
+  [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m")
+	(match_operand:BI 1 "move_operand"         " O,n, c,  c,*r, n,*m,*r"))]
+  ""
+  "@
+   cmp.ne %0, %I0 = r0, r0
+   cmp.eq %0, %I0 = r0, r0
+   #
+   #
+   tbit.nz %0, %I0 = %1, 0
+   adds %0 = %1, r0
+   ld1%O1 %0 = %1%P1
+   st1%Q0 %0 = %1%P0"
+  [(set_attr "type" "A,A,unknown,unknown,I,A,M,M")])
+
+(define_split
+  [(set (match_operand:BI 0 "register_operand" "")
+	(match_operand:BI 1 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+  [(cond_exec (ne (match_dup 1) (const_int 0))
+     (set (match_dup 0) (const_int 1)))
+   (cond_exec (eq (match_dup 1) (const_int 0))
+     (set (match_dup 0) (const_int 0)))]
+  "")
+
+(define_split
+  [(set (match_operand:BI 0 "register_operand" "")
+	(match_operand:BI 1 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+  [(set (match_dup 2) (match_dup 4))
+   (set (match_dup 3) (match_dup 5))
+   (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
+  "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
+   operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
+   operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
+   operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
+
 (define_expand "movqi"
   [(set (match_operand:QI 0 "general_operand" "")
 	(match_operand:QI 1 "general_operand" ""))]
@@ -180,7 +235,7 @@
 (define_insn "*movqicc_astep"
   [(cond_exec
      (match_operator 2 "predicate_operator"
-       [(match_operand:CC 3 "register_operand" "c,c,c,c,c")
+       [(match_operand:BI 3 "register_operand" "c,c,c,c,c")
         (const_int 0)])
      (set (match_operand:QI 0 "register_operand"  "=r,r, r,*f,*f")
 	  (match_operand:QI 1 "nonmemory_operand" "rO,J,*f,rO,*f")))]
@@ -238,7 +293,7 @@
 (define_insn "*movhicc_astep"
   [(cond_exec
      (match_operator 2 "predicate_operator"
-       [(match_operand:CC 3 "register_operand" "c,c,c,c,c")
+       [(match_operand:BI 3 "register_operand" "c,c,c,c,c")
         (const_int 0)])
      (set (match_operand:HI 0 "register_operand"  "=r,r, r,*f,*f")
 	  (match_operand:HI 1 "nonmemory_operand" "rO,J,*f,rO,*f")))]
@@ -296,7 +351,7 @@
 (define_insn "*movsicc_astep"
   [(cond_exec
      (match_operator 2 "predicate_operator"
-       [(match_operand:CC 3 "register_operand" "c,c,c,c,c,c,c,c")
+       [(match_operand:BI 3 "register_operand" "c,c,c,c,c,c,c,c")
         (const_int 0)])
      (set (match_operand:SI 0 "register_operand"  "=r,r,r, r,*f,*f, r,*d")
 	  (match_operand:SI 1 "nonmemory_operand" "rO,J,i,*f,rO,*f,*d,rK")))]
@@ -383,7 +438,7 @@
 (define_insn ""
   [(cond_exec
      (match_operator 2 "predicate_operator"
-       [(match_operand:CC 3 "register_operand" "c,c,c,c,c,c,c,c,c,c,c")
+       [(match_operand:BI 3 "register_operand" "c,c,c,c,c,c,c,c,c,c,c")
         (const_int 0)])
      (set (match_operand:DI 0 "register_operand"
 			      "=r,r,r, r,*f,*f,   r,*b,*e, r,*d")
@@ -719,7 +774,7 @@
 (define_insn "*movsfcc_astep"
   [(cond_exec
      (match_operator 2 "predicate_operator"
-       [(match_operand:CC 3 "register_operand" "c,c,c,c")
+       [(match_operand:BI 3 "register_operand" "c,c,c,c")
         (const_int 0)])
      (set (match_operand:SF 0 "register_operand"  "=f,*r, f,*r")
 	  (match_operand:SF 1 "nonmemory_operand" "fG,fG,*r,*r")))]
@@ -778,7 +833,7 @@
 (define_insn "*movdfcc_astep"
   [(cond_exec
      (match_operator 2 "predicate_operator"
-       [(match_operand:CC 3 "register_operand" "c,c,c,c")
+       [(match_operand:BI 3 "register_operand" "c,c,c,c")
         (const_int 0)])
      (set (match_operand:DF 0 "register_operand"  "=f,*r, f,*r")
 	  (match_operand:DF 1 "nonmemory_operand" "fG,fG,*r,*r")))]
@@ -900,7 +955,7 @@
 (define_insn "*movtfcc_astep"
   [(cond_exec
      (match_operator 2 "predicate_operator"
-       [(match_operand:CC 3 "register_operand" "c")
+       [(match_operand:BI 3 "register_operand" "c")
         (const_int 0)])
      (set (match_operand:TF 0 "register_operand"  "=f")
 	  (match_operand:TF 1 "nonmemory_operand" "fG")))]
@@ -1357,6 +1412,520 @@
 
 ;; ::::::::::::::::::::
 ;; ::
+;; :: 1 bit Integer arithmetic
+;; ::
+;; ::::::::::::::::::::
+
+(define_insn_and_split "andbi3"
+  [(set (match_operand:BI 0 "register_operand" "=c,c,r")
+	(and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
+		(match_operand:BI 2 "register_operand" "c,r,r")))]
+  ""
+  "@
+   #
+   tbit.nz.and.orcm %0, %I0 = %2, 0
+   and %0 = %2, %1"
+  "reload_completed
+   && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
+   && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
+  [(cond_exec (eq (match_dup 2) (const_int 0))
+     (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
+				(match_dup 0))))]
+  ""
+  [(set_attr "type" "unknown,I,A")])
+
+(define_insn_and_split "*andcmbi3"
+  [(set (match_operand:BI 0 "register_operand" "=c,c,r")
+	(and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
+		(match_operand:BI 2 "register_operand" "0,0,r")))]
+  ""
+  "@
+   #
+   tbit.z.and.orcm %0, %I0 = %2, 0
+   andcm %0 = %2, %1"
+  "reload_completed
+   && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
+   && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
+  [(cond_exec (ne (match_dup 1) (const_int 0))
+     (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
+				(match_dup 0))))]
+  ""
+  [(set_attr "type" "unknown,I,A")])
+
+(define_insn_and_split "iorbi3"
+  [(set (match_operand:BI 0 "register_operand" "=c,c,r")
+	(ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
+		(match_operand:BI 2 "register_operand" "c,r,r")))]
+  ""
+  "@
+   #
+   tbit.nz.or.andcm %0, %I0 = %2, 0
+   or %0 = %2, %1"
+  "reload_completed
+   && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
+   && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
+  [(cond_exec (ne (match_dup 2) (const_int 0))
+     (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
+				(match_dup 0))))]
+  ""
+  [(set_attr "type" "unknown,I,A")])
+
+(define_insn_and_split "*iorcmbi3"
+  [(set (match_operand:BI 0 "register_operand" "=c,c")
+	(ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
+		(match_operand:BI 2 "register_operand" "0,0")))]
+  ""
+  "@
+   #
+   tbit.z.or.andcm %0, %I0 = %2, 0"
+  "reload_completed
+   && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
+   && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
+  [(cond_exec (eq (match_dup 1) (const_int 0))
+     (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
+				(match_dup 0))))]
+  ""
+  [(set_attr "type" "unknown,I")])
+
+(define_insn "one_cmplbi2"
+  [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
+	(not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
+   (clobber (match_scratch:BI 2 "=X,X,c,X"))]
+  ""
+  "@
+   tbit.z %0, %I0 = %1, 0
+   xor %0 = 1, %1
+   #
+   #"
+  [(set_attr "type" "I,A,unknown,unknown")])
+
+(define_split
+  [(set (match_operand:BI 0 "register_operand" "")
+	(not:BI (match_operand:BI 1 "register_operand" "")))
+   (clobber (match_scratch:BI 2 ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
+   && rtx_equal_p (operands[0], operands[1])"
+  [(set (match_dup 4) (match_dup 3))
+   (set (match_dup 0) (const_int 1))
+   (cond_exec (ne (match_dup 2) (const_int 0))
+     (set (match_dup 0) (const_int 0)))
+   (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
+  "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
+   operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
+
+(define_split
+  [(set (match_operand:BI 0 "register_operand" "")
+	(not:BI (match_operand:BI 1 "register_operand" "")))
+   (clobber (match_scratch:BI 2 ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
+   && ! rtx_equal_p (operands[0], operands[1])"
+  [(cond_exec (ne (match_dup 1) (const_int 0))
+     (set (match_dup 0) (const_int 0)))
+   (cond_exec (eq (match_dup 1) (const_int 0))
+     (set (match_dup 0) (const_int 1)))
+   (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
+  "")
+
+(define_insn "*cmpsi_and_0"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (match_operator:BI 4 "predicate_operator"
+		  [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
+		   (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpsi_and_1"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (match_operator:BI 3 "signed_inequality_operator"
+		  [(match_operand:SI 2 "gr_register_operand" "r")
+		   (const_int 0)])
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpsi_andnot_0"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (not:BI (match_operator:BI 4 "predicate_operator"
+			 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
+			  (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpsi_andnot_1"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
+			  [(match_operand:SI 2 "gr_register_operand" "r")
+			   (const_int 0)]))
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpdi_and_0"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (match_operator:BI 4 "predicate_operator"
+		  [(match_operand:DI 2 "gr_register_operand" "r")
+		   (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp.%C4.and.orcm %0, %I0 = %3, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpdi_and_1"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (match_operator:BI 3 "signed_inequality_operator"
+		  [(match_operand:DI 2 "gr_register_operand" "r")
+		   (const_int 0)])
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp.%C3.and.orcm %0, %I0 = r0, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpdi_andnot_0"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (not:BI (match_operator:BI 4 "predicate_operator"
+			 [(match_operand:DI 2 "gr_register_operand" "r")
+			  (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp.%C4.or.andcm %I0, %0 = %3, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpdi_andnot_1"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
+			  [(match_operand:DI 2 "gr_register_operand" "r")
+			   (const_int 0)]))
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp.%C3.or.andcm %I0, %0 = r0, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*tbit_and_0"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
+			       (const_int 1))
+		       (const_int 0))
+		(match_operand:BI 3 "register_operand" "0")))]
+  ""
+  "tbit.nz.and.orcm %0, %I0 = %1, 0"
+  [(set_attr "type" "I")])
+
+(define_insn "*tbit_and_1"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
+			       (const_int 1))
+		       (const_int 0))
+		(match_operand:BI 3 "register_operand" "0")))]
+  ""
+  "tbit.z.and.orcm %0, %I0 = %1, 0"
+  [(set_attr "type" "I")])
+
+(define_insn "*tbit_and_2"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (ne:BI (zero_extract:DI
+			 (match_operand:DI 1 "gr_register_operand" "r")
+			 (const_int 1)
+			 (match_operand:DI 2 "const_int_operand" "n"))
+		       (const_int 0))
+		(match_operand:BI 3 "register_operand" "0")))]
+  ""
+  "tbit.nz.and.orcm %0, %I0 = %1, %2"
+  [(set_attr "type" "I")])
+
+(define_insn "*tbit_and_3"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(and:BI (eq:BI (zero_extract:DI
+			 (match_operand:DI 1 "gr_register_operand" "r")
+			 (const_int 1)
+			 (match_operand:DI 2 "const_int_operand" "n"))
+		       (const_int 0))
+		(match_operand:BI 3 "register_operand" "0")))]
+  ""
+  "tbit.z.and.orcm %0, %I0 = %1, %2"
+  [(set_attr "type" "I")])
+
+(define_insn "*cmpsi_or_0"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (match_operator:BI 4 "predicate_operator"
+		  [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
+		   (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpsi_or_1"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (match_operator:BI 3 "signed_inequality_operator"
+		  [(match_operand:SI 2 "gr_register_operand" "r")
+		   (const_int 0)])
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpsi_orcm_0"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
+			 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
+			  (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpsi_orcm_1"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
+			  [(match_operand:SI 2 "gr_register_operand" "r")
+			   (const_int 0)]))
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpdi_or_0"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (match_operator:BI 4 "predicate_operator"
+		  [(match_operand:DI 2 "gr_register_operand" "r")
+		   (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp.%C4.or.andcm %0, %I0 = %3, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpdi_or_1"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (match_operator:BI 3 "signed_inequality_operator"
+		  [(match_operand:DI 2 "gr_register_operand" "r")
+		   (const_int 0)])
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp.%C3.or.andcm %0, %I0 = r0, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpdi_orcm_0"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
+			 [(match_operand:DI 2 "gr_register_operand" "r")
+			  (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp.%C4.and.orcm %I0, %0 = %3, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*cmpdi_orcm_1"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
+			  [(match_operand:DI 2 "gr_register_operand" "r")
+			   (const_int 0)]))
+		(match_operand:BI 1 "register_operand" "0")))]
+  ""
+  "cmp.%C3.and.orcm %I0, %0 = r0, %2"
+  [(set_attr "type" "A")])
+
+(define_insn "*tbit_or_0"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
+			       (const_int 1))
+		       (const_int 0))
+		(match_operand:BI 3 "register_operand" "0")))]
+  ""
+  "tbit.nz.or.andcm %0, %I0 = %1, 0"
+  [(set_attr "type" "I")])
+
+(define_insn "*tbit_or_1"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
+			       (const_int 1))
+		       (const_int 0))
+		(match_operand:BI 3 "register_operand" "0")))]
+  ""
+  "tbit.z.or.andcm %0, %I0 = %1, 0"
+  [(set_attr "type" "I")])
+
+(define_insn "*tbit_or_2"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (ne:BI (zero_extract:DI
+			 (match_operand:DI 1 "gr_register_operand" "r")
+			 (const_int 1)
+			 (match_operand:DI 2 "const_int_operand" "n"))
+		       (const_int 0))
+		(match_operand:BI 3 "register_operand" "0")))]
+  ""
+  "tbit.nz.or.andcm %0, %I0 = %1, %2"
+  [(set_attr "type" "I")])
+
+(define_insn "*tbit_or_3"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ior:BI (eq:BI (zero_extract:DI
+			 (match_operand:DI 1 "gr_register_operand" "r")
+			 (const_int 1)
+			 (match_operand:DI 2 "const_int_operand" "n"))
+		       (const_int 0))
+		(match_operand:BI 3 "register_operand" "0")))]
+  ""
+  "tbit.z.or.andcm %0, %I0 = %1, %2"
+  [(set_attr "type" "I")])
+
+;; Transform test of and/or of setcc into parallel comparisons.
+
+(define_split
+  [(set (match_operand:BI 0 "register_operand" "")
+	(ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
+			      (const_int 0))
+		       (match_operand:DI 3 "register_operand" ""))
+	       (const_int 0)))]
+  ""
+  [(set (match_dup 0)
+	(and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
+		(match_dup 2)))]
+  "")
+
+(define_split
+  [(set (match_operand:BI 0 "register_operand" "")
+	(eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
+			      (const_int 0))
+		       (match_operand:DI 3 "register_operand" ""))
+	       (const_int 0)))]
+  ""
+  [(set (match_dup 0)
+	(and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
+		(match_dup 2)))
+   (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
+	      (clobber (scratch))])]
+  "")
+
+(define_split
+  [(set (match_operand:BI 0 "register_operand" "")
+	(ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
+			      (const_int 0))
+		       (match_operand:DI 3 "register_operand" ""))
+	       (const_int 0)))]
+  ""
+  [(set (match_dup 0) 
+	(ior:BI (ne:BI (match_dup 3) (const_int 0))
+		(match_dup 2)))]
+  "")
+
+(define_split
+  [(set (match_operand:BI 0 "register_operand" "")
+	(eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
+			      (const_int 0))
+		       (match_operand:DI 3 "register_operand" ""))
+	       (const_int 0)))]
+  ""
+  [(set (match_dup 0) 
+	(ior:BI (ne:BI (match_dup 3) (const_int 0))
+		(match_dup 2)))
+   (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
+	      (clobber (scratch))])]
+  "")
+
+;; ??? Incredibly hackish.  Either need four proper patterns with all
+;; the alternatives, or rely on sched1 to split the insn and hope that
+;; nothing bad happens to the comparisons in the meantime.
+;;
+;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
+;; that we're doing height reduction.
+;
+;(define_insn_and_split ""
+;  [(set (match_operand:BI 0 "register_operand" "=c")
+;	(and:BI (and:BI (match_operator:BI 1 "comparison_operator"
+;			  [(match_operand 2 "" "")
+;			   (match_operand 3 "" "")])
+;			(match_operator:BI 4 "comparison_operator"
+;			  [(match_operand 5 "" "")
+;			   (match_operand 6 "" "")]))
+;		(match_dup 0)))]
+;  "flag_schedule_insns"
+;  "#"
+;  ""
+;  [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
+;   (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
+;  "")
+;
+;(define_insn_and_split ""
+;  [(set (match_operand:BI 0 "register_operand" "=c")
+;	(ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
+;			  [(match_operand 2 "" "")
+;			   (match_operand 3 "" "")])
+;			(match_operator:BI 4 "comparison_operator"
+;			  [(match_operand 5 "" "")
+;			   (match_operand 6 "" "")]))
+;		(match_dup 0)))]
+;  "flag_schedule_insns"
+;  "#"
+;  ""
+;  [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
+;   (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
+;  "")
+;
+;(define_split
+;  [(set (match_operand:BI 0 "register_operand" "")
+;	(and:BI (and:BI (match_operator:BI 1 "comparison_operator"
+;			  [(match_operand 2 "" "")
+;			   (match_operand 3 "" "")])
+;			(match_operand:BI 7 "register_operand" ""))
+;		(and:BI (match_operator:BI 4 "comparison_operator"
+;			  [(match_operand 5 "" "")
+;			   (match_operand 6 "" "")])
+;			(match_operand:BI 8 "register_operand" ""))))]
+;  ""
+;  [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
+;   (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
+;			      (match_dup 0)))]
+;  "")
+;
+;(define_split
+;  [(set (match_operand:BI 0 "register_operand" "")
+;	(ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
+;			  [(match_operand 2 "" "")
+;			   (match_operand 3 "" "")])
+;			(match_operand:BI 7 "register_operand" ""))
+;		(ior:BI (match_operator:BI 4 "comparison_operator"
+;			  [(match_operand 5 "" "")
+;			   (match_operand 6 "" "")])
+;			(match_operand:BI 8 "register_operand" ""))))]
+;  ""
+;  [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
+;   (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
+;			      (match_dup 0)))]
+;  "")
+
+;; Try harder to avoid predicate copies by duplicating compares.
+;; Note that we'll have already split the predicate copy, which
+;; is kind of a pain, but oh well.
+
+(define_peephole2
+  [(set (match_operand:BI 0 "register_operand" "")
+	(match_operand:BI 1 "comparison_operator" ""))
+   (set (match_operand:CCI 2 "register_operand" "")
+	(match_operand:CCI 3 "register_operand" ""))
+   (set (match_operand:CCI 4 "register_operand" "")
+	(match_operand:CCI 5 "register_operand" ""))
+   (set (match_operand:BI 6 "register_operand" "")
+	(unspec:BI [(match_dup 6)] 7))]
+  "REGNO (operands[3]) == REGNO (operands[0])
+   && REGNO (operands[4]) == REGNO (operands[0]) + 1
+   && REGNO (operands[4]) == REGNO (operands[2]) + 1
+   && REGNO (operands[6]) == REGNO (operands[2])"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 6) (match_dup 7))]
+  "operands[7] = copy_rtx (operands[1]);")
+
+;; ::::::::::::::::::::
+;; ::
 ;; :: 16 bit Integer arithmetic
 ;; ::
 ;; ::::::::::::::::::::
@@ -1435,7 +2004,7 @@
 	(mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
 		 (match_operand:SI 2 "grfr_register_operand" "f")))]
   ""
-  "xma.l %0 = %1, %2, f0%B0"
+  "xmpy.l %0 = %1, %2%B0"
   [(set_attr "type" "F")])
 
 (define_insn "maddsi4"
@@ -1456,67 +2025,67 @@
 
 (define_expand "abssi2"
   [(set (match_dup 2)
-	(ge:CC (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
+	(ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
    (set (match_operand:SI 0 "gr_register_operand" "")
-	(if_then_else:SI (eq:CC (match_dup 2) (const_int 0))
+	(if_then_else:SI (eq (match_dup 2) (const_int 0))
 			 (neg:SI (match_dup 1))
 			 (match_dup 1)))]
   ""
   "
 {
-  operands[2] = gen_reg_rtx (CCmode);
+  operands[2] = gen_reg_rtx (BImode);
 }")
 
 (define_expand "sminsi3"
   [(set (match_dup 3)
-	(ge:CC (match_operand:SI 1 "gr_register_operand" "")
+	(ge:BI (match_operand:SI 1 "gr_register_operand" "")
 	       (match_operand:SI 2 "gr_register_operand" "")))
    (set (match_operand:SI 0 "gr_register_operand" "")
-	(if_then_else:SI (ne:CC (match_dup 3) (const_int 0))
+	(if_then_else:SI (ne (match_dup 3) (const_int 0))
 			 (match_dup 2) (match_dup 1)))]
   ""
   "
 {
-  operands[3] = gen_reg_rtx (CCmode);
+  operands[3] = gen_reg_rtx (BImode);
 }")
 
 (define_expand "smaxsi3"
   [(set (match_dup 3)
-	(ge:CC (match_operand:SI 1 "gr_register_operand" "")
+	(ge:BI (match_operand:SI 1 "gr_register_operand" "")
 	       (match_operand:SI 2 "gr_register_operand" "")))
    (set (match_operand:SI 0 "gr_register_operand" "")
-	(if_then_else:SI (ne:CC (match_dup 3) (const_int 0))
+	(if_then_else:SI (ne (match_dup 3) (const_int 0))
 			 (match_dup 1) (match_dup 2)))]
   ""
   "
 {
-  operands[3] = gen_reg_rtx (CCmode);
+  operands[3] = gen_reg_rtx (BImode);
 }")
 
 (define_expand "uminsi3"
   [(set (match_dup 3)
-	(geu:CC (match_operand:SI 1 "gr_register_operand" "")
+	(geu:BI (match_operand:SI 1 "gr_register_operand" "")
 		(match_operand:SI 2 "gr_register_operand" "")))
    (set (match_operand:SI 0 "gr_register_operand" "")
-	(if_then_else:SI (ne:CC (match_dup 3) (const_int 0))
+	(if_then_else:SI (ne (match_dup 3) (const_int 0))
 			 (match_dup 2) (match_dup 1)))]
   ""
   "
 {
-  operands[3] = gen_reg_rtx (CCmode);
+  operands[3] = gen_reg_rtx (BImode);
 }")
 
 (define_expand "umaxsi3"
   [(set (match_dup 3)
-	(geu:CC (match_operand:SI 1 "gr_register_operand" "")
+	(geu:BI (match_operand:SI 1 "gr_register_operand" "")
 		(match_operand:SI 2 "gr_register_operand" "")))
    (set (match_operand:SI 0 "gr_register_operand" "")
-	(if_then_else:SI (ne:CC (match_dup 3) (const_int 0))
+	(if_then_else:SI (ne (match_dup 3) (const_int 0))
 			 (match_dup 1) (match_dup 2)))]
   ""
   "
 {
-  operands[3] = gen_reg_rtx (CCmode);
+  operands[3] = gen_reg_rtx (BImode);
 }")
 
 (define_expand "divsi3"
@@ -1651,13 +2220,13 @@
 			  (match_operand:TF 2 "fr_register_operand" "f"))))
    (clobber (match_scratch:TF 4 "=&f"))
    (clobber (match_scratch:TF 5 "=&f"))
-   (clobber (match_scratch:CC 6 "=c"))
+   (clobber (match_scratch:BI 6 "=c"))
    (use (match_operand:TF 3 "fr_register_operand" "f"))]
   "TARGET_INLINE_DIV"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
-	      (set (match_dup 6) (unspec:CC [(match_dup 1) (match_dup 2)] 5))
+	      (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 6) (const_int 0))
      (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
@@ -1747,7 +2316,7 @@
 	(mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
 		 (match_operand:DI 2 "grfr_register_operand" "f")))]
   ""
-  "xma.l %0 = %1, %2, f0%B0"
+  "xmpy.l %0 = %1, %2%B0"
   [(set_attr "type" "F")])
 
 ;; ??? If operand 3 is an eliminable reg, then register elimination causes the
@@ -1823,7 +2392,7 @@
 		     (match_operand:DI 2 "fr_register_operand" "f")))
 	  (const_int 64))))]
   ""
-  "xma.h %0 = %1, %2, f0%B0"
+  "xmpy.h %0 = %1, %2%B0"
   [(set_attr "type" "F")])
 
 (define_insn "umuldi3_highpart"
@@ -1836,7 +2405,7 @@
 		     (match_operand:DI 2 "fr_register_operand" "f")))
 	  (const_int 64))))]
   ""
-  "xma.hu %0 = %1, %2, f0%B0"
+  "xmpy.hu %0 = %1, %2%B0"
   [(set_attr "type" "F")])
 
 (define_insn "negdi2"
@@ -1848,78 +2417,78 @@
 
 (define_expand "absdi2"
   [(set (match_dup 2)
-	(ge:CC (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
+	(ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
    (set (match_operand:DI 0 "gr_register_operand" "")
-	(if_then_else:DI (eq:CC (match_dup 2) (const_int 0))
+	(if_then_else:DI (eq (match_dup 2) (const_int 0))
 			 (neg:DI (match_dup 1))
 			 (match_dup 1)))]
   ""
   "
 {
-  operands[2] = gen_reg_rtx (CCmode);
+  operands[2] = gen_reg_rtx (BImode);
 }")
 
 (define_expand "smindi3"
   [(set (match_dup 3)
-	(ge:CC (match_operand:DI 1 "gr_register_operand" "")
+	(ge:BI (match_operand:DI 1 "gr_register_operand" "")
 	       (match_operand:DI 2 "gr_register_operand" "")))
    (set (match_operand:DI 0 "gr_register_operand" "")
-	(if_then_else:DI (ne:CC (match_dup 3) (const_int 0))
+	(if_then_else:DI (ne (match_dup 3) (const_int 0))
 			 (match_dup 2) (match_dup 1)))]
   ""
   "
 {
-  operands[3] = gen_reg_rtx (CCmode);
+  operands[3] = gen_reg_rtx (BImode);
 }")
 
 (define_expand "smaxdi3"
   [(set (match_dup 3)
-	(ge:CC (match_operand:DI 1 "gr_register_operand" "")
+	(ge:BI (match_operand:DI 1 "gr_register_operand" "")
 	       (match_operand:DI 2 "gr_register_operand" "")))
    (set (match_operand:DI 0 "gr_register_operand" "")
-	(if_then_else:DI (ne:CC (match_dup 3) (const_int 0))
+	(if_then_else:DI (ne (match_dup 3) (const_int 0))
 			 (match_dup 1) (match_dup 2)))]
   ""
   "
 {
-  operands[3] = gen_reg_rtx (CCmode);
+  operands[3] = gen_reg_rtx (BImode);
 }")
 
 (define_expand "umindi3"
   [(set (match_dup 3)
-	(geu:CC (match_operand:DI 1 "gr_register_operand" "")
+	(geu:BI (match_operand:DI 1 "gr_register_operand" "")
 		(match_operand:DI 2 "gr_register_operand" "")))
    (set (match_operand:DI 0 "gr_register_operand" "")
-	(if_then_else:DI (ne:CC (match_dup 3) (const_int 0))
+	(if_then_else:DI (ne (match_dup 3) (const_int 0))
 			 (match_dup 2) (match_dup 1)))]
   ""
   "
 {
-  operands[3] = gen_reg_rtx (CCmode);
+  operands[3] = gen_reg_rtx (BImode);
 }")
 
 (define_expand "umaxdi3"
   [(set (match_dup 3)
-	(geu:CC (match_operand:DI 1 "gr_register_operand" "")
+	(geu:BI (match_operand:DI 1 "gr_register_operand" "")
 		(match_operand:DI 2 "gr_register_operand" "")))
    (set (match_operand:DI 0 "gr_register_operand" "")
-	(if_then_else:DI (ne:CC (match_dup 3) (const_int 0))
+	(if_then_else:DI (ne (match_dup 3) (const_int 0))
 			 (match_dup 1) (match_dup 2)))]
   ""
   "
 {
-  operands[3] = gen_reg_rtx (CCmode);
+  operands[3] = gen_reg_rtx (BImode);
 }")
 
 (define_expand "ffsdi2"
   [(set (match_dup 6)
-	(eq:CC (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
+	(eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
    (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
    (set (match_dup 5) (const_int 0))
    (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
    (set (match_dup 4) (unspec:DI [(match_dup 3)] 8))
    (set (match_operand:DI 0 "gr_register_operand" "")
-	(if_then_else:DI (ne:CC (match_dup 6) (const_int 0))
+	(if_then_else:DI (ne (match_dup 6) (const_int 0))
 			 (match_dup 5) (match_dup 4)))]
   ""
   "
@@ -1928,7 +2497,7 @@
   operands[3] = gen_reg_rtx (DImode);
   operands[4] = gen_reg_rtx (DImode);
   operands[5] = gen_reg_rtx (DImode);
-  operands[6] = gen_reg_rtx (CCmode);
+  operands[6] = gen_reg_rtx (BImode);
 }")
 
 (define_insn "*popcnt"
@@ -2041,12 +2610,12 @@
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:TF 4 "=&f"))
    (clobber (match_scratch:TF 5 "=&f"))
-   (clobber (match_scratch:CC 6 "=c"))]
+   (clobber (match_scratch:BI 6 "=c"))]
   "TARGET_INLINE_DIV_LAT"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
-	      (set (match_dup 6) (unspec:CC [(match_dup 1) (match_dup 2)] 5))
+	      (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 6) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -2099,12 +2668,12 @@
 			  (match_operand:TF 2 "fr_register_operand" "f"))))
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:TF 4 "=f"))
-   (clobber (match_scratch:CC 5 "=c"))]
+   (clobber (match_scratch:BI 5 "=c"))]
   "TARGET_INLINE_DIV_THR"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
-	      (set (match_dup 5) (unspec:CC [(match_dup 1) (match_dup 2)] 5))
+	      (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 5) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -2268,12 +2837,12 @@
 		(match_operand:SF 2 "fr_register_operand" "f")))
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:TF 4 "=f"))
-   (clobber (match_scratch:CC 5 "=c"))]
+   (clobber (match_scratch:BI 5 "=c"))]
   "TARGET_INLINE_DIV_LAT"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
-	      (set (match_dup 5) (unspec:CC [(match_dup 7) (match_dup 8)] 5))
+	      (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 5) (const_int 0))
      (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6)))
@@ -2322,12 +2891,12 @@
 		(match_operand:SF 2 "fr_register_operand" "f")))
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:TF 4 "=f"))
-   (clobber (match_scratch:CC 5 "=c"))]
+   (clobber (match_scratch:BI 5 "=c"))]
   "TARGET_INLINE_DIV_THR"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
-	      (set (match_dup 5) (unspec:CC [(match_dup 7) (match_dup 8)] 5))
+	      (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 5) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -2573,12 +3142,12 @@
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:TF 4 "=&f"))
    (clobber (match_scratch:TF 5 "=&f"))
-   (clobber (match_scratch:CC 6 "=c"))]
+   (clobber (match_scratch:BI 6 "=c"))]
   "TARGET_INLINE_DIV_LAT"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
-	      (set (match_dup 6) (unspec:CC [(match_dup 8) (match_dup 9)] 5))
+	      (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] 5))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 6) (const_int 0))
      (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7)))
@@ -2650,12 +3219,12 @@
 		(match_operand:DF 2 "fr_register_operand" "f")))
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:DF 4 "=f"))
-   (clobber (match_scratch:CC 5 "=c"))]
+   (clobber (match_scratch:BI 5 "=c"))]
   "TARGET_INLINE_DIV_THR"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
-	      (set (match_dup 5) (unspec:CC [(match_dup 7) (match_dup 8)] 5))
+	      (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 5) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -3046,12 +3615,12 @@
    (clobber (match_scratch:TF 4 "=&f"))
    (clobber (match_scratch:TF 5 "=&f"))
    (clobber (match_scratch:TF 6 "=&f"))
-   (clobber (match_scratch:CC 7 "=c"))]
+   (clobber (match_scratch:BI 7 "=c"))]
   "TARGET_INLINE_DIV_LAT"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
-	      (set (match_dup 7) (unspec:CC [(match_dup 1) (match_dup 2)] 5))
+	      (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 7) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -3123,12 +3692,12 @@
 		(match_operand:TF 2 "fr_register_operand" "f")))
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:TF 4 "=&f"))
-   (clobber (match_scratch:CC 5 "=c"))]
+   (clobber (match_scratch:BI 5 "=c"))]
   "TARGET_INLINE_DIV_THR"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
-	      (set (match_dup 5) (unspec:CC [(match_dup 1) (match_dup 2)] 5))
+	      (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 5) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -3200,8 +3769,8 @@
   [(set (match_operand:TF 0 "fr_register_operand" "=f")
 	(div:TF (const_int 1)
 		(match_operand:TF 3 "fr_register_operand" "f")))
-   (set (match_operand:CC 1 "register_operand" "=c")
-	(unspec:CC [(match_operand:TF 2 "fr_register_operand" "f")
+   (set (match_operand:BI 1 "register_operand" "=c")
+	(unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
 		    (match_dup 3)] 5))
    (use (match_operand:SI 4 "const_int_operand" ""))]
   ""
@@ -3484,6 +4053,18 @@
 ;; ::
 ;; ::::::::::::::::::::
 
+(define_expand "cmpbi"
+  [(set (cc0)
+        (compare (match_operand:BI 0 "register_operand" "")
+  		 (match_operand:BI 1 "const_int_operand" "")))]
+  ""
+  "
+{
+  ia64_compare_op0 = operands[0];
+  ia64_compare_op1 = operands[1];
+  DONE;
+}")
+
 (define_expand "cmpsi"
   [(set (cc0)
         (compare (match_operand:SI 0 "gr_register_operand" "")
@@ -3545,8 +4126,8 @@
 }")
 
 (define_insn "*cmpsi_normal"
-  [(set (match_operand:CC 0 "register_operand" "=c")
-	(match_operator:CC 1 "normal_comparison_operator"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(match_operator:BI 1 "normal_comparison_operator"
 	   [(match_operand:SI 2 "gr_register_operand" "r")
 	    (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
   ""
@@ -3554,8 +4135,8 @@
   [(set_attr "type" "A")])
 
 (define_insn "*cmpsi_adjusted"
-  [(set (match_operand:CC 0 "register_operand" "=c")
-	(match_operator:CC 1 "adjusted_comparison_operator"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(match_operator:BI 1 "adjusted_comparison_operator"
 	   [(match_operand:SI 2 "gr_register_operand" "r")
 	    (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
   ""
@@ -3563,17 +4144,17 @@
   [(set_attr "type" "A")])
 
 (define_insn "*cmpdi_normal"
-  [(set (match_operand:CC 0 "register_operand" "=c")
-	(match_operator:CC 1 "normal_comparison_operator"
-	   [(match_operand:DI 2 "gr_register_operand" "r")
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(match_operator:BI 1 "normal_comparison_operator"
+	   [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
 	    (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
   ""
-  "cmp.%C1 %0, %I0 = %3, %2"
+  "cmp.%C1 %0, %I0 = %3, %r2"
   [(set_attr "type" "A")])
 
 (define_insn "*cmpdi_adjusted"
-  [(set (match_operand:CC 0 "register_operand" "=c")
-	(match_operator:CC 1 "adjusted_comparison_operator"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(match_operator:BI 1 "adjusted_comparison_operator"
 	   [(match_operand:DI 2 "gr_register_operand" "r")
 	    (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
   ""
@@ -3581,8 +4162,8 @@
   [(set_attr "type" "A")])
 
 (define_insn "*cmpsf_internal"
-  [(set (match_operand:CC 0 "register_operand" "=c")
-	(match_operator:CC 1 "comparison_operator"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(match_operator:BI 1 "comparison_operator"
 	   [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
 	    (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
   ""
@@ -3590,8 +4171,8 @@
   [(set_attr "type" "F")])
 
 (define_insn "*cmpdf_internal"
-  [(set (match_operand:CC 0 "register_operand" "=c")
-	(match_operator:CC 1 "comparison_operator"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(match_operator:BI 1 "comparison_operator"
 	   [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
 	    (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
   ""
@@ -3599,8 +4180,8 @@
   [(set_attr "type" "F")])
 
 (define_insn "*cmptf_internal"
-  [(set (match_operand:CC 0 "register_operand" "=c")
-	(match_operator:CC 1 "comparison_operator"
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(match_operator:BI 1 "comparison_operator"
 		   [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")
 		    (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
   ""
@@ -3610,8 +4191,8 @@
 ;; ??? Can this pattern be generated?
 
 (define_insn "*bit_zero"
-  [(set (match_operand:CC 0 "register_operand" "=c")
-	(eq:CC (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
 				(const_int 1)
 				(match_operand:DI 2 "immediate_operand" "n"))
 	       (const_int 0)))]
@@ -3620,65 +4201,14 @@
   [(set_attr "type" "I")])
 
 (define_insn "*bit_one"
-  [(set (match_operand:CC 0 "register_operand" "=c")
-	(ne:CC (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
+  [(set (match_operand:BI 0 "register_operand" "=c")
+	(ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
 				(const_int 1)
 				(match_operand:DI 2 "immediate_operand" "n"))
 	       (const_int 0)))]
   ""
   "tbit.nz %0, %I0 = %1, %2"
   [(set_attr "type" "I")])
-
-;; ??? We also need this if we run out of PR regs and need to spill some.
-
-;; ??? We need this if a CCmode value does not get allocated to a hard
-;; register.  This happens if we cse/gcse a CCmode value across a call, and the
-;; function has a nonlocal goto.  This is because global does not allocate
-;; call crossing pseudos to hard registers when current_function_has_
-;; nonlocal_goto is true.  This is relatively common for C++ programs that
-;; use exceptions.  See ia64_secondary_reload_class.
-
-;; We use a define_expand here so that cse/gcse/combine can't accidentally
-;; create movcc insns.  If this was a named define_insn, we would not be able
-;; to make it conditional on reload.
-
-(define_expand "movcc"
-  [(set (match_operand:CC 0 "nonimmediate_operand" "")
-	(match_operand:CC 1 "move_operand" ""))]
-  ""
-  "
-{
-  if (! reload_in_progress && ! reload_completed)
-    FAIL;
-}")
-
-(define_insn "*movcc_internal"
-  [(set (match_operand:CC 0 "nonimmediate_operand" "=r,c,r,m")
-	(match_operand:CC 1 "move_operand" "c,r,m,r"))]
-  "reload_in_progress || reload_completed"
-  "@
-   #
-   cmp4.ne %0, %I0 = %1, r0
-   ld4%O1 %0 = %1%P1
-   st4%Q0 %0 = %1%P0"
-  [(set_attr "type" "unknown,A,M,M")])
-
-(define_split
-  [(set (match_operand:CC 0 "register_operand" "")
-	(match_operand:CC 1 "register_operand" ""))]
-  "reload_completed
-   && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
-  [(set (match_dup 2)
-	(if_then_else:DI (ne:CC (match_dup 1) (const_int 0))
-			 (const_int 1)
-			 (match_dup 2)))
-   (set (match_dup 2)
-	(if_then_else:DI (ne:CC (match_dup 1) (const_int 0))
-			 (match_dup 2)
-			 (const_int 0)))]
-  "operands[2] = gen_rtx_SUBREG (DImode, operands[0], 0);")
-
 
 ;; ::::::::::::::::::::
 ;; ::
@@ -3687,213 +4217,105 @@
 ;; ::::::::::::::::::::
 
 (define_expand "beq"
-  [(set (match_dup 1)
-	(eq:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (EQ, VOIDmode);")
 
 (define_expand "bne"
-  [(set (match_dup 1)
-	(ne:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (NE, VOIDmode);")
 
 (define_expand "blt"
-  [(set (match_dup 1)
-	(lt:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (LT, VOIDmode);")
 
 (define_expand "ble"
-  [(set (match_dup 1)
-	(le:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (LE, VOIDmode);")
 
 (define_expand "bgt"
-  [(set (match_dup 1)
-	(gt:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (GT, VOIDmode);")
 
 (define_expand "bge"
-  [(set (match_dup 1)
-	(ge:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (GE, VOIDmode);")
 
 (define_expand "bltu"
-  [(set (match_dup 1)
-	(ltu:CC (match_dup 2)
-		(match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (LTU, VOIDmode);")
 
 (define_expand "bleu"
-  [(set (match_dup 1)
-	(leu:CC (match_dup 2)
-		(match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (LEU, VOIDmode);")
 
 (define_expand "bgtu"
-  [(set (match_dup 1)
-	(gtu:CC (match_dup 2)
-		(match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (GTU, VOIDmode);")
 
 (define_expand "bgeu"
-  [(set (match_dup 1)
-	(geu:CC (match_dup 2)
-		(match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (GEU, VOIDmode);")
 
 (define_expand "bunordered"
-  [(set (match_dup 1)
-	(unordered:CC (match_dup 2)
-		      (match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);")
 
 (define_expand "bordered"
-  [(set (match_dup 1)
-	(ordered:CC (match_dup 2)
-		      (match_dup 3)))
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);")
 
 (define_insn "*br_true"
   [(set (pc)
 	(if_then_else (match_operator 0 "predicate_operator"
-			[(match_operand:CC 1 "register_operand" "c")
+			[(match_operand:BI 1 "register_operand" "c")
 			 (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
@@ -3905,7 +4327,7 @@
 (define_insn "*br_false"
   [(set (pc)
 	(if_then_else (match_operator 0 "predicate_operator"
-			[(match_operand:CC 1 "register_operand" "c")
+			[(match_operand:BI 1 "register_operand" "c")
 			 (const_int 0)])
 		      (pc)
 		      (label_ref (match_operand 2 "" ""))))]
@@ -3957,214 +4379,95 @@
 ;; ::::::::::::::::::::
 
 (define_expand "seq"
-  [(set (match_dup 1)
-	(eq:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (EQ, DImode);")
 
 (define_expand "sne"
-  [(set (match_dup 1)
-	(ne:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (NE, DImode);")
 
 (define_expand "slt"
-  [(set (match_dup 1)
-	(lt:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (LT, DImode);")
 
 (define_expand "sle"
-  [(set (match_dup 1)
-	(le:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (LE, DImode);")
 
 (define_expand "sgt"
-  [(set (match_dup 1)
-	(gt:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (GT, DImode);")
 
 (define_expand "sge"
-  [(set (match_dup 1)
-	(ge:CC (match_dup 2)
-	       (match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (GE, DImode);")
 
 (define_expand "sltu"
-  [(set (match_dup 1)
-	(ltu:CC (match_dup 2)
-		(match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (LTU, DImode);")
 
 (define_expand "sleu"
-  [(set (match_dup 1)
-	(leu:CC (match_dup 2)
-		(match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (LEU, DImode);")
 
 (define_expand "sgtu"
-  [(set (match_dup 1)
-	(gtu:CC (match_dup 2)
-		(match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (GTU, DImode);")
 
 (define_expand "sgeu"
-  [(set (match_dup 1)
-	(geu:CC (match_dup 2)
-		(match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (GEU, DImode);")
 
 (define_expand "sunordered"
-  [(set (match_dup 1)
-	(unordered:CC (match_dup 2)
-		      (match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (UNORDERED, DImode);")
 
 (define_expand "sordered"
-  [(set (match_dup 1)
-	(ordered:CC (match_dup 2)
-		      (match_dup 3)))
-   (set (match_operand:DI 0 "gr_register_operand" "")
-	(ne:DI (match_dup 1) (const_int 0)))]
+  [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = ia64_compare_op0;
-  operands[3] = ia64_compare_op1;
-}")
+  "operands[1] = ia64_expand_compare (ORDERED, DImode);")
 
 ;; Don't allow memory as destination here, because cmov/cmov/st is more
 ;; efficient than mov/mov/cst/cst.
 
 (define_insn_and_split "*sne_internal"
   [(set (match_operand:DI 0 "gr_register_operand" "=r")
-	(ne:DI (match_operand:CC 1 "register_operand" "c")
+	(ne:DI (match_operand:BI 1 "register_operand" "c")
 	       (const_int 0)))]
   ""
   "#"
   "reload_completed"
-  [(set (match_dup 0)
-	(if_then_else:DI (ne:CC (match_dup 1) (const_int 0))
-			 (const_int 1)
-			 (match_dup 0)))
-   (set (match_dup 0)
-	(if_then_else:DI (ne:CC (match_dup 1) (const_int 0))
-			 (match_dup 0)
-			 (const_int 0)))]
+  [(cond_exec (ne (match_dup 1) (const_int 0))
+     (set (match_dup 0) (const_int 1)))
+   (cond_exec (eq (match_dup 1) (const_int 0))
+     (set (match_dup 0) (const_int 0)))]
   ""
   [(set_attr "type" "unknown")])
 
-;; ??? Unknown if this can be matched.
-
 (define_insn_and_split "*seq_internal"
   [(set (match_operand:DI 0 "gr_register_operand" "=r")
-	(eq:DI (match_operand:CC 1 "register_operand" "c")
+	(eq:DI (match_operand:BI 1 "register_operand" "c")
 	       (const_int 0)))]
   ""
   "#"
   "reload_completed"
-  [(set (match_dup 0)
-	(if_then_else:DI (eq:CC (match_dup 1) (const_int 0))
-			 (const_int 1)
-			 (match_dup 0)))
-   (set (match_dup 0)
-	(if_then_else:DI (eq:CC (match_dup 1) (const_int 0))
-			 (match_dup 0)
-			 (const_int 0)))]
+  [(cond_exec (ne (match_dup 1) (const_int 0))
+     (set (match_dup 0) (const_int 0)))
+   (cond_exec (eq (match_dup 1) (const_int 0))
+     (set (match_dup 0) (const_int 1)))]
   ""
   [(set_attr "type" "unknown")])
-
 
 ;; ::::::::::::::::::::
 ;; ::
@@ -4180,45 +4483,49 @@
 
 ;; Errata 72 workaround.
 (define_insn "*cmovdi_internal_astep"
-  [(set (match_operand:DI 0 "nonimmediate_operand"
-		"=r,*f,Q,*b,r,*f,Q,*b,r,*f,Q,*b")
+  [(set (match_operand:DI 0 "register_operand"
+		"=r,*f,*b,r,*f,*b,r,*f,*b")
 	(if_then_else:DI
-	  (match_operator:CC 4 "predicate_operator"
-	    [(match_operand:CC 1 "register_operand"
-			       "c,c,c,c,c,c,c,c,c,c,c,c")
+	  (match_operator 4 "predicate_operator"
+	    [(match_operand:BI 1 "register_operand"
+			       "c,c,c,c,c,c,c,c,c")
 	     (const_int 0)])
-	  (match_operand:DI 2 "general_operand"
-		"0,0,0,0,ri*f*b,rO,*f,r,ri*f*b,rO,*f,r")
-	  (match_operand:DI 3 "general_operand"
-		"ri*f*b,rO,*f,r,0,0,0,0,ri*f*b,rO,*f,r")))]
-  "TARGET_A_STEP"
+	  (match_operand:DI 2 "move_operand"
+		"0,0,0,ri*f*b,rO,r,ri*f*b,rO,r")
+	  (match_operand:DI 3 "move_operand"
+		"ri*f*b,rO,r,0,0,0,ri*f*b,rO,r")))]
+  "TARGET_A_STEP
+   && ia64_move_ok (operands[0], operands[2])
+   && ia64_move_ok (operands[0], operands[3])"
   "* abort ();"
   [(set_attr "predicable" "no")])
 
 (define_insn "*cmovdi_internal"
-  [(set (match_operand:DI 0 "nonimmediate_operand"
+  [(set (match_operand:DI 0 "destination_operand"
 		"=r,m,*f,Q,*b,*d*e,r,m,*f,Q,*b,*d*e,r,m,*f,Q,*b,*d*e")
 	(if_then_else:DI
-	  (match_operator:CC 4 "predicate_operator"
-	    [(match_operand:CC 1 "register_operand"
+	  (match_operator 4 "predicate_operator"
+	    [(match_operand:BI 1 "register_operand"
 			       "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
 	     (const_int 0)])
-	  (match_operand:DI 2 "general_operand"
+	  (match_operand:DI 2 "move_operand"
 		"0,0,0,0,0,0,rim*f*b*d*e,rO,rOQ,*f,rO,rK,rim*f*b*d*e,rO,rOQ,*f,rO,rK")
-	  (match_operand:DI 3 "general_operand"
+	  (match_operand:DI 3 "move_operand"
 		"rim*f*b*d*e,rO,rOQ,*f,rO,rK,0,0,0,0,0,0,rim*f*b*d*e,rO,rOQ,*f,rO,rK")))]
-  "! TARGET_A_STEP"
+  "! TARGET_A_STEP
+   && ia64_move_ok (operands[0], operands[2])
+   && ia64_move_ok (operands[0], operands[3])"
   "* abort ();"
   [(set_attr "predicable" "no")])
 
 (define_split
-  [(set (match_operand 0 "nonimmediate_operand" "")
+  [(set (match_operand 0 "destination_operand" "")
 	(if_then_else
-	  (match_operator:CC 4 "predicate_operator"
-	    [(match_operand:CC 1 "register_operand" "")
+	  (match_operator 4 "predicate_operator"
+	    [(match_operand:BI 1 "register_operand" "")
 	     (const_int 0)])
-	  (match_operand 2 "general_operand" "")
-	  (match_operand 3 "general_operand" "")))]
+	  (match_operand 2 "move_operand" "")
+	  (match_operand 3 "move_operand" "")))]
   "reload_completed"
   [(const_int 0)]
   "
@@ -4233,7 +4540,7 @@
   if (! rtx_equal_p (operands[0], operands[3]))
     {
       tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
-			    CCmode, operands[1], const0_rtx);
+			    VOIDmode, operands[1], const0_rtx);
       tmp = gen_rtx_COND_EXEC (VOIDmode, tmp,
 			       gen_rtx_SET (VOIDmode, operands[0],
 					    operands[3]));
@@ -4247,8 +4554,8 @@
 (define_insn "*absdi2_internal"
   [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
 	(if_then_else:DI
-	  (match_operator:CC 4 "predicate_operator"
-	    [(match_operand:CC 1 "register_operand" "c,c")
+	  (match_operator 4 "predicate_operator"
+	    [(match_operand:BI 1 "register_operand" "c,c")
 	     (const_int 0)])
 	  (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
 	  (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
@@ -4260,8 +4567,8 @@
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
 	(if_then_else:DI
-	  (match_operator:CC 4 "predicate_operator"
-	    [(match_operand:CC 1 "register_operand" "c,c")
+	  (match_operator 4 "predicate_operator"
+	    [(match_operand:BI 1 "register_operand" "c,c")
 	     (const_int 0)])
 	  (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
 	  (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
@@ -4275,8 +4582,8 @@
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
 	(if_then_else:DI
-	  (match_operator:CC 4 "predicate_operator"
-	    [(match_operand:CC 1 "register_operand" "c,c")
+	  (match_operator 4 "predicate_operator"
+	    [(match_operand:BI 1 "register_operand" "c,c")
 	     (const_int 0)])
 	  (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
 	  (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
@@ -4290,7 +4597,7 @@
   "
 {
   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
-				CCmode, operands[1], const0_rtx);
+				VOIDmode, operands[1], const0_rtx);
 }")
 
 ;;
@@ -4298,38 +4605,40 @@
 ;;
 
 (define_insn "*cmovsi_internal_astep"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,*f,r,*f,r,*f")
+  [(set (match_operand:SI 0 "register_operand" "=r,*f,r,*f,r,*f")
 	(if_then_else:SI
-	  (match_operator:CC 4 "predicate_operator"
-	    [(match_operand:CC 1 "register_operand" "c,c,c,c,c,c")
+	  (match_operator 4 "predicate_operator"
+	    [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c")
 	     (const_int 0)])
-	  (match_operand:SI 2 "general_operand"
-		    "0,0,ri*f,rO,ri*f,rO")
-	  (match_operand:SI 3 "general_operand"
-		    "ri*f,rO,0,0,ri*f,rO")))]
-  "TARGET_A_STEP"
+	  (match_operand:SI 2 "move_operand" "0,0,ri*f,rO,ri*f,rO")
+	  (match_operand:SI 3 "move_operand" "ri*f,rO,0,0,ri*f,rO")))]
+  "TARGET_A_STEP
+   && ia64_move_ok (operands[0], operands[2])
+   && ia64_move_ok (operands[0], operands[3])"
   "* abort ();"
   [(set_attr "predicable" "no")])
 
 (define_insn "*cmovsi_internal"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,*f,r,m,*f,r,m,*f")
+  [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f")
 	(if_then_else:SI
-	  (match_operator:CC 4 "predicate_operator"
-	    [(match_operand:CC 1 "register_operand" "c,c,c,c,c,c,c,c,c")
+	  (match_operator 4 "predicate_operator"
+	    [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
 	     (const_int 0)])
-	  (match_operand:SI 2 "general_operand"
+	  (match_operand:SI 2 "move_operand"
 		    "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
-	  (match_operand:SI 3 "general_operand"
+	  (match_operand:SI 3 "move_operand"
 		    "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
-  "! TARGET_A_STEP"
+  "! TARGET_A_STEP
+   && ia64_move_ok (operands[0], operands[2])
+   && ia64_move_ok (operands[0], operands[3])"
   "* abort ();"
   [(set_attr "predicable" "no")])
 
 (define_insn "*abssi2_internal"
   [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
 	(if_then_else:SI
-	  (match_operator:CC 4 "predicate_operator"
-	    [(match_operand:CC 1 "register_operand" "c,c")
+	  (match_operator 4 "predicate_operator"
+	    [(match_operand:BI 1 "register_operand" "c,c")
 	     (const_int 0)])
 	  (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
 	  (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
@@ -4341,8 +4650,8 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
 	(if_then_else:SI
-	  (match_operator:CC 4 "predicate_operator"
-	    [(match_operand:CC 1 "register_operand" "c,c")
+	  (match_operator 4 "predicate_operator"
+	    [(match_operand:BI 1 "register_operand" "c,c")
 	     (const_int 0)])
 	  (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
 	  (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
@@ -4356,8 +4665,8 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
 	(if_then_else:SI
-	  (match_operator:CC 4 "predicate_operator"
-	    [(match_operand:CC 1 "register_operand" "c,c")
+	  (match_operator 4 "predicate_operator"
+	    [(match_operand:BI 1 "register_operand" "c,c")
 	     (const_int 0)])
 	  (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
 	  (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
@@ -4371,7 +4680,7 @@
   "
 {
   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
-				CCmode, operands[1], const0_rtx);
+				VOIDmode, operands[1], const0_rtx);
 }")
 
 
@@ -4712,7 +5021,7 @@
 (define_insn "*return_true"
   [(set (pc)
 	(if_then_else (match_operator 0 "predicate_operator"
-			[(match_operand:CC 1 "register_operand" "c")
+			[(match_operand:BI 1 "register_operand" "c")
 			 (const_int 0)])
 		      (return)
 		      (pc)))]
@@ -4724,7 +5033,7 @@
 (define_insn "*return_false"
   [(set (pc)
 	(if_then_else (match_operator 0 "predicate_operator"
-			[(match_operand:CC 1 "register_operand" "c")
+			[(match_operand:BI 1 "register_operand" "c")
 			 (const_int 0)])
 		      (pc)
 		      (return)))]
@@ -5122,13 +5431,14 @@
 
 (define_cond_exec
   [(match_operator 0 "predicate_operator"
-     [(match_operand:CC 1 "register_operand" "c")
+     [(match_operand:BI 1 "register_operand" "c")
       (const_int 0)])]
   ""
   "(%J0)")
 
 (define_insn "pred_rel_mutex"
-  [(unspec_volatile [(match_operand:CC 0 "register_operand" "c")] 7)]
+  [(set (match_operand:BI 0 "register_operand" "+c")
+       (unspec:BI [(match_dup 0)] 7))]
   ""
   ".pred.rel.mutex %0, %I0"
   [(set_attr "type" "unknown")