* config/ia64/ia64.c (reg_or_5bit_operand): New.

        (ia64_depz_field_mask): New.
        * config/ia64/ia64.h (CONSTRAINT_OK_FOR_R): New.
        (PREDICATE_CODES): Update.
        * config/ia64/ia64.md: Update commentary.
        (depz_internal): New.
        (ashlsi3): Implement directly.
        (ashrsi3, lshrsi3): Simplify; rely on extv and extzv for constants.
        (ashldi3): Use shladd.
        * config/ia64/ia64-protos.h: Update.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@35802 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 61 insertions, 82 deletions

diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 0734936d1e9..e0173e6a344 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -1113,9 +1113,6 @@
 ;; ::
 ;; ::::::::::::::::::::
 
-;; ??? It would be useful to have SImode versions of the extract and insert
-;; patterns.
-
 (define_insn "extv"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extract:DI (match_operand:DI 1 "register_operand" "r")
@@ -1229,6 +1226,21 @@
   "dep %0 = %3, %0, %2, %1"
   [(set_attr "type" "I")])
 
+;; Combine doesn't like to create bitfield insertions into zero.
+(define_insn "*depz_internal"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
+			   (match_operand:DI 2 "const_int_operand" "n"))
+		(match_operand:DI 3 "const_int_operand" "n")))]
+  "CONST_OK_FOR_M (INTVAL (operands[2]))
+   && ia64_depz_field_mask (operands[3], operands[2]) > 0"
+  "*
+{
+  operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
+  return \"%,dep.z %0 = %1, %2, %3\";
+}"
+  [(set_attr "type" "I")])
+
 (define_insn "shift_mix4left"
   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
 			 (const_int 32) (const_int 0))
@@ -1238,9 +1250,6 @@
   "#"
   [(set_attr "type" "unknown")])
 
-;; ??? Need to emit an instruction group barrier here because this gets split
-;; after md_reorg.
-
 (define_split
   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
 			 (const_int 32) (const_int 0))
@@ -2003,89 +2012,59 @@
 ;; ::
 ;; ::::::::::::::::::::
 
-;; There is no sign-extend form of dep, so we only get 32 bits of valid result
-;; instead of 64 like the patterns below.
-
-;; Using a predicate that accepts only constants doesn't work, because optabs
-;; will load the operand into a register and call the pattern if the predicate
-;; did not accept it on the first try.  So we use nonmemory_operand and then
-;; verify that we have an appropriate constant in the expander.
-
-(define_expand "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashift:SI (match_operand:SI 1 "register_operand" "")
-		   (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (! shift_32bit_count_operand (operands[2], SImode))
-    FAIL;
-}")
-
-(define_insn "*ashlsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "r")
-		   (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
+(define_insn "ashlsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(ashift:SI (match_operand:SI 1 "register_operand" "r,r,r")
+		   (match_operand:SI 2 "reg_or_5bit_operand" "R,n,r")))]
   ""
-  "dep.z %0 = %1, %2, %E2"
-  [(set_attr "type" "I")])
-
-;; This is really an extract, but this is how combine canonicalizes the
-;; operation.
+  "@
+   shladd %0 = %1, %2, r0
+   dep.z %0 = %1, %2, %E2
+   shl %0 = %1, %2"
+  [(set_attr "type" "A,I,I")])
 
 (define_expand "ashrsi3"
-  [(set (match_dup 3)
-	(ashiftrt:DI (sign_extend:DI
-		      (match_operand:SI 1 "register_operand" ""))
-		     (match_operand:DI 2 "nonmemory_operand" "")))
-   (set (match_operand:SI 0 "register_operand" "") (match_dup 4))]
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
+		     (match_operand:SI 2 "reg_or_5bit_operand" "")))]
   ""
   "
 {
-  if (! shift_32bit_count_operand (operands[2], SImode))
-    FAIL;
-
-  operands[3] = gen_reg_rtx (DImode);
-  operands[4] = gen_lowpart (SImode, operands[3]);
+  rtx subtarget = gen_reg_rtx (DImode);
+  if (GET_CODE (operands[2]) == CONST_INT)
+    emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
+			 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
+  else
+    {
+      emit_insn (gen_extendsidi2 (subtarget, operands[1]));
+      emit_insn (gen_ashrdi3 (subtarget, subtarget,
+			      gen_lowpart (DImode, operands[2])));
+    }
+  emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
+  DONE;
 }")
 
-(define_insn "*ashrsi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashiftrt:DI (sign_extend:DI
-		      (match_operand:SI 1 "register_operand" "r"))
-		     (match_operand:DI 2 "shift_32bit_count_operand" "n")))]
-  ""
-  "extr %0 = %1, %2, %E2"
-  [(set_attr "type" "I")])
-
-;; This is really an extract, but this is how combine canonicalizes the
-;; operation.
-
 (define_expand "lshrsi3"
-  [(set (match_dup 3)
-	(lshiftrt:DI (zero_extend:DI
-		      (match_operand:SI 1 "register_operand" ""))
-		     (match_operand:DI 2 "nonmemory_operand" "")))
-   (set (match_operand:SI 0 "register_operand" "") (match_dup 4))]
+  [(set (match_operand:SI 0 "register_operand" "")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
+		     (match_operand:SI 2 "reg_or_5bit_operand" "")))]
   ""
   "
 {
-  if (! shift_32bit_count_operand (operands[2], SImode))
-    FAIL;
-
-  operands[3] = gen_reg_rtx (DImode);
-  operands[4] = gen_lowpart (SImode, operands[3]);
+  rtx subtarget = gen_reg_rtx (DImode);
+  if (GET_CODE (operands[2]) == CONST_INT)
+    emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
+			  GEN_INT (32 - INTVAL (operands[2])), operands[2]));
+  else
+    {
+      emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
+      emit_insn (gen_lshrdi3 (subtarget, subtarget,
+			      gen_lowpart (DImode, operands[2])));
+    }
+  emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
+  DONE;
 }")
 
-(define_insn "*lshrsi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(lshiftrt:DI (zero_extend:DI
-		      (match_operand:SI 1 "register_operand" "r"))
-		     (match_operand:DI 2 "shift_32bit_count_operand" "n")))]
-  ""
-  "extr.u %0 = %1, %2, %E2"
-  [(set_attr "type" "I")])
-
 ;; Use mix4.r/shr to implement rotrsi3.  We only get 32 bits of valid result
 ;; here, instead of 64 like the patterns above.
 
@@ -2102,11 +2081,9 @@
 {
   if (! shift_32bit_count_operand (operands[2], SImode))
     FAIL;
-
   operands[3] = gen_reg_rtx (DImode);
   operands[4] = gen_lowpart (SImode, operands[3]);
 }")
-
 
 ;; ::::::::::::::::::::
 ;; ::
@@ -2115,12 +2092,14 @@
 ;; ::::::::::::::::::::
 
 (define_insn "ashldi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (match_operand:DI 1 "register_operand" "r")
-		   (match_operand:DI 2 "reg_or_6bit_operand" "rM")))]
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(ashift:DI (match_operand:DI 1 "register_operand" "r,r")
+		   (match_operand:DI 2 "reg_or_6bit_operand" "R,rM")))]
   ""
-  "shl %0 = %1, %2"
-  [(set_attr "type" "I")])
+  "@
+   shladd %0 = %1, %2, r0
+   shl %0 = %1, %2"
+  [(set_attr "type" "A,I")])
 
 ;; ??? Maybe combine this with the multiply and add instruction?