* config/ia64/ia64-protos.h: Remove duplicates. Update

	for massive code rearrangements.
	* config/ia64/ia64.c (ia64_arpfs_regno): Remove.
	(ia64_rp_regno, ia64_fp_regno, ia64_input_regs): Remove.
	(ia64_local_regs, ia64_need_regstk): Remove.
	(ar_ccv_reg_operand): New.
	(ia64_gp_save_reg): New.
	(struct ia64_frame_info): Combine most of the size elements;
	add new gr save elements.
	(find_gr_spill): New.
	(next_scratch_gr_reg): New.
	(mark_reg_gr_used_mask): New.
	(ia64_compute_frame_size): Rewrite.  Allocate special AR regs
	to GR backing store regs when possible.
	(ia64_initial_elimination_offset): New.
	(ia64_rap_fp_offset): Remove.
	(save_restore_insns): Remove.
	(setup_spill_pointers): New.
	(finish_spill_pointers): New.
	(spill_restore_mem): New.
	(do_spill, do_restore): New.
	(ia64_expand_prologue): Rewrite to use them.
	(ia64_expand_epilogue): Likewise.
	(ia64_direct_return): Update for current_frame_info changes.
	(ia64_function_prologue): Simplify .prologue emission.  Emit
	.spill when needed.
	(ia64_setup_incoming_varargs): Don't ever emit rtl.
	(ia64_dbx_register_number): New.
	(ia64_initialize_trampoline): New.
	(ia64_secondary_reload_class): Request GR_REGS for integer
	arithmetic destined for FR_REGS.
	(ia64_init_machine_status): Don't reset return_address_pointer_rtx.
	(ia64_mark_machine_status): Mark ia64_gp_save.
	(rws_access_regno): Rename from rws_access_reg; don't treat
	predicates specially.
	(rws_access_reg): New.  Update all callers.
	(rtx_needs_barrier): Remove dead unspecs.
	(ia64_epilogue_uses): Mark ar.pfs and ar.unat live on exit.
	(ia64_encode_section_info): Silence signed/unsigned warnings.
	(spill_offset, sp_offset, spill_offset_emitted): Remove.
	(tmp_reg, tmp_saved): Remove.
	(process_set): Rewrite to expect complicated bits via
	REG_FRAME_RELATED_EXPR.
	(ia64_expand_fetch_and_op): Use emit_move_insn; be explicit
	in the use of ar.ccv; never set RTX_UNCHANGING_P.
	(ia64_expand_op_and_fetch): Likewise.
	(ia64_expand_compare_and_swap): Likewise.
	(ia64_expand_builtin): Likewise.
	* config/ia64/ia64.h (AR_UNAT_REGNUM): New.
	(FIRST_PSEUDO_REGISTER): Update.
	(AR_M_REGNO_P): Update.
	(FIXED_REGS): Don't mark three local registers as used.
	(EXTRA_CC_MODES): New.
	(SELECT_CC_MODE): New.
	(HARD_REGNO_NREGS): Allow DImode in p0; handle CCImode.
	(HARD_REGNO_MODE_OK): Disallow CCImode from non-predicates.
	(FRAME_GROWS_DOWNWARD): Unset.
	(STARTING_FRAME_OFFSET): Zero.
	(ELIMINABLE_REGS): Eliminate from the soft to hard frame pointer.
	(INITIAL_ELIMINATION_OFFSET): Defer to out of line function.
	(HARD_FRAME_POINTER_REGNUM): New.
	(CAN_DEBUG_WITHOUT_FP): Define.
	(TRAMPOLINE_TEMPLATE): Remove.
	(TRAMPOLINE_SIZE): Lower to 32.
	(TRAMPOLINE_ALIGNMENT): Lower to 64.
	(INITIALIZE_TRAMPOLINE): Defer to out of line function.
	(PREDICATE_CODES): Update.
	(struct machine_function): Add ia64_gp_save.
	* config/ia64/ia64.md: Purge unused unspecs.
	(movsi patterns): Allow moves to/from AR_M_REGS.
	(movdi patterns): Allow moves to/from p0.
	(call patterns): Move most setjmp hackery to ia64_gp_save_reg.
	(gr_spill, gr_restore): Indicate ar.unat read/written.
	(nonlocal_goto): Don't pass old frame_pointer.
	(nonlocal_goto_receiver): Remove.
	(exception_receiver): New.
	(builtin_setjmp_setup): New.
	(builtin_setjmp_receiver): New.
	* config/ia64/lib1funcs.asm (__ia64_save_stack_nonlocal): Bundle.
	(__ia64_nonlocal_goto): Bundle.  Don't kill r7.
	(__ia64_restore_stack_nonlocal): Likewise.
	(__ia64_trampoline): New.
	* config/ia64/sysv4.h (DBX_REGISTER_NUMBER): Defer to out of line
	function.
	* config/ia64/t-ia64 (LIB1ASMFUNCS): Add __trampoline.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@35568 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 195 insertions, 278 deletions

diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 4cc442bfa0d..3bce4e2cda3 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -59,15 +59,9 @@
 ;;	2	gr_restore
 ;;	3	fr_spill
 ;;	4	fr_restore
-;;	5	pr_spill
 ;;	8	popcnt
-;;	9	unat_spill
-;;	10	unat_restore
+;;	12	mf
 ;;	13	cmpxchg_acq
-;;	14	val_compare_and_swap
-;;	16	lock_test_and_set
-;;	17	op_and_fetch
-;;	18	fetch_and_op
 ;;	19	fetchadd_acq
 ;;	20	bsp_value
 ;;	21	flushrs
@@ -76,10 +70,7 @@
 ;;	0	alloc
 ;;	1	blockage
 ;;	2	insn_group_barrier
-;;	3	flush_cache
-;;	4	pfs_restore
 ;;	5	set_bsp
-;;	6	pr_restore
 ;;	7	pred.rel.mutex
 
 ;; ::::::::::::::::::::
@@ -302,10 +293,10 @@
 (define_insn "*movsicc_astep"
   [(cond_exec
      (match_operator 2 "predicate_operator"
-       [(match_operand:CC 3 "register_operand" "c,c,c,c,c,c")
+       [(match_operand:CC 3 "register_operand" "c,c,c,c,c,c,c,c")
         (const_int 0)])
-     (set (match_operand:SI 0 "register_operand"  "=r,r,r, r,*f,*f")
-	  (match_operand:SI 1 "nonmemory_operand" "rO,J,i,*f,rO,*f")))]
+     (set (match_operand:SI 0 "register_operand"  "=r,r,r, r,*f,*f, r,*d")
+	  (match_operand:SI 1 "nonmemory_operand" "rO,J,i,*f,rO,*f,*d,rO")))]
   "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
   "@
    (%J2) mov %0 = %r1
@@ -313,13 +304,15 @@
    (%J2) movl %0 = %1
    (%J2) getf.sig %0 = %1
    (%J2) setf.sig %0 = %r1
-   (%J2) mov %0 = %1"
-  [(set_attr "type" "A,A,L,M,M,F")
+   (%J2) mov %0 = %1
+   (%J2) mov %0 = %1
+   (%J2) mov %0 = %r1"
+  [(set_attr "type" "A,A,L,M,M,F,M,M")
    (set_attr "predicable" "no")])
 
 (define_insn "*movsi_internal_astep"
-  [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f")
-	(match_operand:SI 1 "move_operand"        "rO,J,i,m,rO,*f,rO,*f"))]
+  [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
+	(match_operand:SI 1 "move_operand"        "rO,J,i,m,rO,*f,rO,*f,*d,rO"))]
   "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
   "@
   mov %0 = %r1
@@ -329,13 +322,15 @@
   st4%Q0 %0 = %r1%P0
   getf.sig %0 = %1
   setf.sig %0 = %r1
-  mov %0 = %1"
-  [(set_attr "type" "A,A,L,M,M,M,M,F")
+  mov %0 = %1
+  mov %0 = %1
+  mov %0 = %r1"
+  [(set_attr "type" "A,A,L,M,M,M,M,F,M,M")
    (set_attr "predicable" "no")])
 
 (define_insn "*movsi_internal"
-  [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f")
-	(match_operand:SI 1 "move_operand"        "rO,J,i,m,rO,*f,rO,*f"))]
+  [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
+	(match_operand:SI 1 "move_operand"        "rO,J,i,m,rO,*f,rO,*f,*d,rO"))]
   "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
   "@
   mov %0 = %r1
@@ -345,8 +340,10 @@
   st4%Q0 %0 = %r1%P0
   getf.sig %0 = %1
   setf.sig %0 = %r1
-  mov %0 = %1"
-  [(set_attr "type" "A,A,L,M,M,M,M,F")])
+  mov %0 = %1
+  mov %0 = %1
+  mov %0 = %r1"
+  [(set_attr "type" "A,A,L,M,M,M,M,F,M,M")])
 
 (define_expand "movdi"
   [(set (match_operand:DI 0 "general_operand" "")
@@ -412,9 +409,9 @@
 
 (define_insn "*movdi_internal_astep"
   [(set (match_operand:DI 0 "destination_operand"
-			    "=r,r,r,r, m, r,*f,*f,*f, Q,   r,*b*e, r,*d")
+		    "=r,r,r,r, m, r,*f,*f,*f, Q,   r,*b*e, r,*d, r,*c")
 	(match_operand:DI 1 "move_operand"
-			    "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e,  rO,*d,rO"))]
+		    "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e,  rO,*d,rO,*c,rO"))]
   "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
   "*
 {
@@ -432,7 +429,9 @@
     \"mov %0 = %1\",
     \"mov %0 = %r1\",
     \"mov %0 = %1\",
-    \"mov %0 = %r1\"
+    \"mov %0 = %r1\",
+    \"mov %0 = pr\",
+    \"mov pr = %1, -1\"
   };
 
   if (which_alternative == 2 && ! TARGET_NO_PIC
@@ -441,14 +440,14 @@
 
   return alt[which_alternative];
 }"
-  [(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,M,M")
+  [(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,M,M,I,I")
    (set_attr "predicable" "no")])
 
 (define_insn "*movdi_internal"
   [(set (match_operand:DI 0 "destination_operand"
-			    "=r,r,r,r, m, r,*f,*f,*f, Q,   r,*b*e, r,*d")
+		    "=r,r,r,r, m, r,*f,*f,*f, Q,   r,*b*e, r,*d, r,*c")
 	(match_operand:DI 1 "move_operand"
-			    "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e,  rO,*d,rO"))]
+		    "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e,  rO,*d,rO,*c,rO"))]
   "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
   "*
 {
@@ -466,7 +465,9 @@
     \"%,mov %0 = %1\",
     \"%,mov %0 = %r1\",
     \"%,mov %0 = %1\",
-    \"%,mov %0 = %r1\"
+    \"%,mov %0 = %r1\",
+    \"mov %0 = pr\",
+    \"mov pr = %1, -1\"
   };
 
   if (which_alternative == 2 && ! TARGET_NO_PIC
@@ -475,7 +476,7 @@
 
   return alt[which_alternative];
 }"
-  [(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,M,M")])
+  [(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,M,M,I,I")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -2780,16 +2781,16 @@
 ;; Errata 72 workaround.
 (define_insn "*cmovdi_internal_astep"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-		"=r,*f,Q,*b*d*e,r,*f,Q,*b*d*e,r,*f,Q,*b*d*e")
+		"=r,*f,Q,*b,r,*f,Q,*b,r,*f,Q,*b")
 	(if_then_else:DI
 	  (match_operator:CC 4 "predicate_operator"
 	    [(match_operand:CC 1 "register_operand"
 			       "c,c,c,c,c,c,c,c,c,c,c,c")
 	     (const_int 0)])
 	  (match_operand:DI 2 "general_operand"
-		"0,0,0,0,ri*f*b*d*e,rO,*f,r,ri*f*b*d*e,rO,*f,r")
+		"0,0,0,0,ri*f*b,rO,*f,r,ri*f*b,rO,*f,r")
 	  (match_operand:DI 3 "general_operand"
-		"ri*f*b*d*e,rO,*f,r,0,0,0,0,ri*f*b*d*e,rO,*f,r")))]
+		"ri*f*b,rO,*f,r,0,0,0,0,ri*f*b,rO,*f,r")))]
   "TARGET_A_STEP"
   "* abort ();"
   [(set_attr "predicable" "no")])
@@ -3012,9 +3013,6 @@
   else if (TARGET_CONST_GP)
     emit_call_insn (gen_call_internal (addr, operands[1],
 				       gen_rtx_REG (DImode, R_BR (0))));
-  /* ??? This is an unsatisfying solution.  Should rethink.  */
-  else if (setjmp_operand (addr, mode))
-    emit_insn (gen_setjmp_call_pic (addr, operands[1]));
   else
     emit_insn (gen_call_pic (addr, operands[1]));
 
@@ -3033,32 +3031,11 @@
   ""
   "
 {
-  operands[2] = gen_reg_rtx (DImode);
+  operands[2] = ia64_gp_save_reg (0);
   operands[3] = gen_reg_rtx (DImode);
   operands[4] = gen_reg_rtx (DImode);
 }")
 
-;; We can't save GP in a pseudo if we are calling setjmp, because pseudos
-;; won't be restored by longjmp.  For now, we save it in r4.
-
-;; ??? It would be more efficient to save this directly into a stack slot.
-;; Unfortunately, the stack slot address gets cse'd across the setjmp call
-;; because the NOTE_INSN_SETJMP note is in the wrong place.
-
-;; ??? This is an unsatisfying solution.  Should rethink.
-
-(define_expand "setjmp_call_pic"
-  [(set (match_dup 2) (reg:DI 1))
-   (parallel [(call (mem:DI (match_operand 0 "" "")) (match_operand 1 "" ""))
-	      (use (reg:DI 1))
-	      (clobber (reg:DI 320))])
-   (set (reg:DI 1) (match_dup 2))]
-  ""
-  "
-{
-  operands[2] = gen_rtx_REG (DImode, GR_REG (4));
-}")
-
 ;; ??? Saving/restoring the GP register is not needed if we are calling
 ;; a function in the same module.
 
@@ -3071,7 +3048,9 @@
   ""
   "
 {
-  operands[2] = gen_reg_rtx (DImode);
+  /* ??? Using setjmp_operand is an unsatisfying solution.  Should rethink.  */
+  operands[2] = ia64_gp_save_reg (setjmp_operand (XEXP (operands[0], 0),
+						  VOIDmode));
 }")
 
 (define_insn "call_internal"
@@ -3129,9 +3108,6 @@
   else if (TARGET_CONST_GP)
     emit_call_insn (gen_call_value_internal (operands[0], addr, operands[2],
 					     gen_rtx_REG (DImode, R_BR (0))));
-  /* ??? This is an unsatisfying solution.  Should rethink.  */
-  else if (setjmp_operand (addr, mode))
-    emit_insn (gen_setjmp_call_value_pic (operands[0], addr, operands[2]));
   /* This is for HFA returns.  */
   else if (GET_CODE (operands[0]) == PARALLEL)
     emit_insn (gen_call_multiple_values_pic (operands[0], addr, operands[2]));
@@ -3154,7 +3130,7 @@
   ""
   "
 {
-  operands[3] = gen_reg_rtx (DImode);
+  operands[3] = ia64_gp_save_reg (0);
   operands[4] = gen_reg_rtx (DImode);
   operands[5] = gen_reg_rtx (DImode);
 }")
@@ -3177,7 +3153,7 @@
   int i;
   rtx call;
 
-  operands[3] = gen_reg_rtx (DImode);
+  operands[3] = ia64_gp_save_reg (0);
   operands[4] = gen_reg_rtx (DImode);
   operands[5] = gen_reg_rtx (DImode);
 
@@ -3203,29 +3179,6 @@
 
 }")
 
-;; We can't save GP in a pseudo if we are calling setjmp, because pseudos
-;; won't be restored by longjmp.  For now, we save it in r4.
-
-;; ??? It would be more efficient to save this directly into a stack slot.
-;; Unfortunately, the stack slot address gets cse'd across the setjmp call
-;; because the NOTE_INSN_SETJMP note is in the wrong place.
-
-;; ??? This is an unsatisfying solution.  Should rethink.
-
-(define_expand "setjmp_call_value_pic"
-  [(set (match_dup 3) (reg:DI 1))
-   (parallel [(set (match_operand 0 "" "")
-		   (call (mem:DI (match_operand 1 "" ""))
-			 (match_operand 2 "" "")))
-	      (use (reg:DI 1))
-	      (clobber (reg:DI 320))])
-   (set (reg:DI 1) (match_dup 3))]
-  ""
-  "
-{
-  operands[3] = gen_rtx_REG (DImode, GR_REG (4));
-}")
-
 ;; ??? Saving/restoring the GP register is not needed if we are calling
 ;; a function in the same module.
 
@@ -3240,7 +3193,9 @@
   ""
   "
 {
-  operands[3] = gen_reg_rtx (DImode);
+  /* ??? Using setjmp_operand is an unsatisfying solution.  Should rethink.  */
+  operands[3] = ia64_gp_save_reg (setjmp_operand (XEXP (operands[1], 0),
+						  VOIDmode));
 }")
 
 ;; ??? Saving/restoring the GP register is not needed if we are calling
@@ -3261,7 +3216,7 @@
   int i;
   rtx call;
 
-  operands[4] = gen_reg_rtx (DImode);
+  operands[4] = ia64_gp_save_reg (0);
 
   call = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (DImode, operands[1]),
 		       operands[2]);
@@ -3478,16 +3433,36 @@
   [(set_attr "type" "M")
    (set_attr "predicable" "no")])
 
-(define_insn "gr_spill"
+;; Modifies ar.unat
+(define_expand "gr_spill"
+  [(parallel
+     [(set (match_operand:DI 0 "memory_operand" "=m")
+	   (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))
+      (clobber (match_dup 2))])]
+  ""
+  "operands[2] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
+
+(define_insn "*gr_spill_internal"
   [(set (match_operand:DI 0 "memory_operand" "=m")
-	(unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
+	(unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))
+   (clobber (match_operand:DI 2 "register_operand" ""))]
   ""
   "st8.spill %0 = %1%P0"
   [(set_attr "type" "M")])
 
-(define_insn "gr_restore"
+;; Reads ar.unat
+(define_expand "gr_restore"
+  [(parallel
+     [(set (match_operand:DI 0 "register_operand" "=r")
+	   (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] 2))
+      (use (match_dup 2))])]
+  ""
+  "operands[2] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
+
+(define_insn "*gr_restore_internal"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] 2))]
+	(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] 2))
+   (use (match_operand:DI 2 "register_operand" ""))]
   ""
   "ld8.fill %0 = %1%P1"
   [(set_attr "type" "M")])
@@ -3506,47 +3481,6 @@
   "ldf.fill %0 = %1%P1"
   [(set_attr "type" "M")])
 
-(define_insn "pr_spill"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(unspec:DI [(const_int 0)] 5))]
-  ""
-  "mov %0 = pr"
-  [(set_attr "type" "I")])
-
-;; ??? This is volatile to prevent it from being moved before a conditional
-;; expression that calculates the return value.
-
-(define_insn "pr_restore"
-  [(unspec_volatile [(const_int 0)] 6)
-   (use (match_operand:DI 0 "register_operand" "r"))]
-  ""
-  "mov pr = %0, -1"
-  [(set_attr "type" "I")])
-
-;; ??? This is volatile to prevent it from being moved before a call.
-;; Should instead add a ar.pfs hard register which is call clobbered.
-
-(define_insn "pfs_restore"
-  [(unspec_volatile [(const_int 0)] 4)
-   (use (match_operand:DI 0 "register_operand" "r"))]
-  ""
-  "mov ar.pfs = %0"
-  [(set_attr "type" "I")])
-
-(define_insn "unat_spill"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(unspec:DI [(const_int 0)] 9))]
-  ""
-  "mov %0 = ar.unat"
-  [(set_attr "type" "M")])
-
-(define_insn "unat_restore"
-  [(unspec [(const_int 0)] 10)
-   (use (match_operand:DI 0 "register_operand" "r"))]
-  ""
-  "mov ar.unat = %0"
-  [(set_attr "type" "M")])
-
 (define_insn "bsp_value"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(unspec:DI [(const_int 0)] 20))]
@@ -3624,31 +3558,39 @@
   ""
   "
 {
-  if (GET_CODE (operands[0]) != REG)
-    operands[0] = force_reg (Pmode, operands[0]);
-  emit_move_insn (virtual_stack_vars_rtx, operands[0]);
-  emit_insn (gen_rtx_USE (VOIDmode, frame_pointer_rtx));
-  emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
-  emit_insn (gen_rtx_USE (VOIDmode, static_chain_rtx));
   emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
-		     0, VOIDmode, 4,
-		     operands[0], Pmode, operands[1], Pmode,
+		     0, VOIDmode, 3,
+		     operands[1], Pmode,
 		     copy_to_reg (XEXP (operands[2], 0)), Pmode,
 		     operands[3], Pmode);
   emit_barrier ();
   DONE;
 }")
 
-;; ??? We need this because the function __ia64_nonlocal_goto can't easily
-;; access the FP which is currently stored in a local register.  Maybe move
-;; the FP to a global register to avoid this problem?
+;; Restore the GP after the exception/longjmp.  The preceeding call will
+;; have tucked it away.
+(define_expand "exception_receiver"
+  [(set (reg:DI 1) (match_dup 0))]
+  ""
+  "operands[0] = ia64_gp_save_reg (0);")
 
-(define_expand "nonlocal_goto_receiver"
-  [(use (const_int 0))]
+;; The rest of the setjmp processing happens with the nonlocal_goto expander.
+;; ??? This is not tested.
+(define_expand "builtin_setjmp_setup"
+  [(use (match_operand:DI 0 "" ""))]
   ""
   "
 {
-  emit_move_insn (frame_pointer_rtx, gen_rtx_REG (DImode, GR_REG (7)));
+  emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1)));
+  DONE;
+}")
+
+(define_expand "builtin_setjmp_receiver"
+  [(use (match_operand:DI 0 "" ""))]
+  ""
+  "
+{
+  emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0));
   DONE;
 }")
 
@@ -3677,20 +3619,7 @@
 
   cfun->machine->ia64_eh_epilogue_sp = sp;
   cfun->machine->ia64_eh_epilogue_bsp = bsp;
-
 }")
-
-;; This flushes at least 64 bytes starting from the address pointed
-;; to by operand[0].
-
-;; ??? This should be a define expand.
-
-(define_insn "flush_cache"
-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "=&r")] 3)]
-  ""
-  "fc %0\;;;\;adds %0=31,%0\;;;\;fc %0\;;;\;sync.i\;srlz.i"
-  [(set_attr "type" "unknown")
-   (set_attr "predicable" "no")])
 
 ;; Builtin apply support.
 
@@ -3710,20 +3639,6 @@
 
 ;;; Intrinsics support.
 
-(define_insn "ccv_restore_si"
-  [(unspec [(const_int 0)] 11)
-   (use (match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "mov ar.ccv = %0"
-  [(set_attr "type" "M")])
-
-(define_insn "ccv_restore_di"
-  [(unspec [(const_int 0)] 11)
-   (use (match_operand:DI 0 "register_operand" "r"))]
-  ""
-  "mov ar.ccv = %0"
-  [(set_attr "type" "M")])
-
 (define_insn "mf"
   [(unspec [(match_operand:BLK 0 "memory_operand" "m")] 12)]
   ""
@@ -3749,50 +3664,50 @@
 (define_insn "cmpxchg_acq_si"
   [(set (match_operand:SI 0 "register_operand" "=r")
         (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 13))]
+                    (match_operand:SI 2 "register_operand" "r")
+		    (match_operand:SI 3 "ar_ccv_reg_operand" "")] 13))]
   ""
-  "cmpxchg4.acq %0 = %1, %2, ar.ccv"
+  "cmpxchg4.acq %0 = %1, %2, %3"
   [(set_attr "type" "M")])
 
 (define_insn "cmpxchg_acq_di"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 13))]
+                    (match_operand:DI 2 "register_operand" "r")
+                    (match_operand:DI 3 "ar_ccv_reg_operand" "")] 13))]
   ""
-  "cmpxchg8.acq %0 = %1, %2, ar.ccv"
+  "cmpxchg8.acq %0 = %1, %2, %3"
   [(set_attr "type" "M")])
 
 (define_expand "val_compare_and_swap_si"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")
-                    (match_operand:SI 3 "register_operand" "r")] 14))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")
+   (match_operand:SI 3 "register_operand" "")]
   ""
   "
 {
-  rtx tmp_reg = gen_rtx_REG (DImode, GR_REG(0));
-  rtx target = gen_rtx_MEM (BLKmode, tmp_reg);
-  RTX_UNCHANGING_P (target) = 1;
-  emit_insn (gen_ccv_restore_si (operands[2]));
+  rtx target = gen_rtx_MEM (BLKmode, gen_rtx_REG (DImode, GR_REG (1)));
+  rtx ccv = gen_rtx_REG (SImode, AR_CCV_REGNUM);
+  emit_move_insn (ccv, operands[2]);
   emit_insn (gen_mf (target));
-  emit_insn (gen_cmpxchg_acq_si (operands[0], operands[1], operands[3]));
+  emit_insn (gen_cmpxchg_acq_si (operands[0], operands[1], operands[3], ccv));
   DONE;
 }")
 
 (define_expand "val_compare_and_swap_di"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")
-                    (match_operand:DI 3 "register_operand" "r")] 14))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")
+   (match_operand:DI 3 "register_operand" "")]
   ""
   "
 {
-  rtx tmp_reg = gen_rtx_REG (DImode, GR_REG(0));
-  rtx target = gen_rtx_MEM (BLKmode, tmp_reg);
-  RTX_UNCHANGING_P (target) = 1;
-  emit_insn (gen_ccv_restore_di (operands[2]));
+  rtx target = gen_rtx_MEM (BLKmode, gen_rtx_REG (DImode, GR_REG (1)));
+  rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
+  emit_move_insn (ccv, operands[2]);
   emit_insn (gen_mf (target));
-  emit_insn (gen_cmpxchg_acq_di (operands[0], operands[1], operands[3]));
+  emit_insn (gen_cmpxchg_acq_di (operands[0], operands[1], operands[3], ccv));
   DONE;
 }")
 
@@ -3815,9 +3730,9 @@
   [(set_attr "type" "M")])
 
 (define_expand "lock_test_and_set_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 16))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {
@@ -3826,9 +3741,9 @@
 }")
 
 (define_expand "lock_test_and_set_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 16))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -3837,9 +3752,9 @@
 }")
 
 (define_expand "fetch_and_add_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "nonmemory_operand" "")] 18))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "nonmemory_operand" "")]
   ""
   "
 {
@@ -3851,7 +3766,8 @@
       if (x == -16 || x == -8 || x == -4 || x == -1 ||
           x ==  16 || x ==  8 || x ==  4 || x ==  1)
         {
-          emit_insn (gen_fetchadd_acq_si (operands[0], operands[1], operands[2]));
+          emit_insn (gen_fetchadd_acq_si (operands[0], operands[1],
+					  operands[2]));
           DONE;
         }
     }
@@ -3861,9 +3777,9 @@
 }")
 
 (define_expand "fetch_and_sub_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 18))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {
@@ -3872,9 +3788,9 @@
 }")
 
 (define_expand "fetch_and_or_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 18))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {
@@ -3883,9 +3799,9 @@
 }")
 
 (define_expand "fetch_and_and_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 18))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {
@@ -3894,9 +3810,9 @@
 }")
 
 (define_expand "fetch_and_xor_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 18))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {
@@ -3905,9 +3821,9 @@
 }")
 
 (define_expand "fetch_and_nand_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 18))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {
@@ -3916,9 +3832,9 @@
 }")
 
 (define_expand "fetch_and_add_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "nonmemory_operand" "")] 18))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "nonmemory_operand" "")]
   ""
   "
 {
@@ -3930,7 +3846,8 @@
       if (x == -16 || x == -8 || x == -4 || x == -1 ||
           x ==  16 || x ==  8 || x ==  4 || x ==  1)
         {
-          emit_insn (gen_fetchadd_acq_di (operands[0], operands[1], operands[2]));
+          emit_insn (gen_fetchadd_acq_di (operands[0], operands[1],
+					  operands[2]));
           DONE;
         }
     }
@@ -3940,9 +3857,9 @@
 }")
 
 (define_expand "fetch_and_sub_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 18))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -3951,9 +3868,9 @@
 }")
 
 (define_expand "fetch_and_or_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 18))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -3962,9 +3879,9 @@
 }")
 
 (define_expand "fetch_and_and_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 18))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -3973,9 +3890,9 @@
 }")
 
 (define_expand "fetch_and_xor_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 18))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -3984,9 +3901,9 @@
 }")
 
 (define_expand "fetch_and_nand_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 18))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -3995,9 +3912,9 @@
 }")
 
 (define_expand "add_and_fetch_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 17))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -4006,9 +3923,9 @@
 }")
 
 (define_expand "sub_and_fetch_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 17))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -4017,9 +3934,9 @@
 }")
 
 (define_expand "or_and_fetch_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 17))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -4028,9 +3945,9 @@
 }")
 
 (define_expand "and_and_fetch_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 17))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -4039,9 +3956,9 @@
 }")
 
 (define_expand "xor_and_fetch_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 17))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -4050,9 +3967,9 @@
 }")
 
 (define_expand "nand_and_fetch_di"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-                    (match_operand:DI 2 "register_operand" "r")] 17))]
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
   "
 {
@@ -4061,9 +3978,9 @@
 }")
 
 (define_expand "add_and_fetch_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 17))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {
@@ -4072,9 +3989,9 @@
 }")
 
 (define_expand "sub_and_fetch_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 17))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {
@@ -4083,9 +4000,9 @@
 }")
 
 (define_expand "or_and_fetch_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 17))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {
@@ -4094,9 +4011,9 @@
 }")
 
 (define_expand "and_and_fetch_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 17))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {
@@ -4105,9 +4022,9 @@
 }")
 
 (define_expand "xor_and_fetch_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 17))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {
@@ -4116,9 +4033,9 @@
 }")
 
 (define_expand "nand_and_fetch_si"
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
-                    (match_operand:SI 2 "register_operand" "r")] 17))]
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "memory_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
   ""
   "
 {