* config/ia64/ia64.c (TARGET_VECTOR_MODE_SUPPORTED_P): New.

        (ia64_const_ok_for_letter_p): New.
        (ia64_const_double_ok_for_letter_p): New.
        (ia64_extra_constraint): New.
        (ia64_expand_vecint_compare): New.
        (ia64_expand_vcondu_v2si): New.
        (ia64_expand_vecint_cmov): New.
        (ia64_expand_vecint_minmax): New.
        (ia64_print_operand): Add 'v'.
        (ia64_preferred_reload_class): New.
        (ia64_vector_mode_supported_p): New.
        * config/ia64/ia64.h (UNITS_PER_SIMD_WORD): New.
        (PREFERRED_RELOAD_CLASS): Move to function.
        (CONST_OK_FOR_LETTER_P): Move to function.
        (CONST_DOUBLE_OK_FOR_LETTER_P): Move to function.
        (CONSTRAINT_OK_FOR_Q, CONSTRAINT_OK_FOR_R): Remove.
        (CONSTRAINT_OK_FOR_S, CONSTRAINT_OK_FOR_T): Remove.
        (EXTRA_CONSTRAINT): Move to function.
        * config/ia64/ia64.md: Include vect.md.
        (itanium_class): Add mmalua.
        (type): Handle it.
        * config/ia64/itanium1.md (1_mmalua): New.  Add it to bypasses.
        (1b_mmalua): New.
        * config/ia64/itanium2.md (2_mmalua, 2b_mmalua): Similarly.
        * config/ia64/predicates.md (gr_reg_or_0_operand): Accept any
        CONST0_RTX.
        (const_int_2bit_operand): New.
        (fr_reg_or_0_operand): New.
        * config/ia64/ia64-modes.def: Add vector modes.
        * config/ia64/ia64-protos.h: Update.
        * config/ia64/vect.md: New file.

        * gcc.dg/vect/vect.exp: Enable for ia64.
        * lib/target-supports.exp (check_effective_target_vect_int): Likewise.
        (check_effective_target_vect_float): Likewise.
        (check_effective_target_vect_no_align): Likewise.
        * gcc.dg/vect/vect-30.c: XFAIL for vect_no_align.
        * gcc.dg/vect/vect-8.c: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@92862 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 16 insertions, 7 deletions

diff --git a/gcc/config/ia64/itanium2.md b/gcc/config/ia64/itanium2.md
index b78b6165354..ad24d19931e 100644
--- a/gcc/config/ia64/itanium2.md
+++ b/gcc/config/ia64/itanium2.md
@@ -786,6 +786,10 @@
   (and (and (eq_attr "cpu" "itanium2")
             (eq_attr "itanium_class" "ilog"))
        (eq (symbol_ref "bundling_p") (const_int 0))) "2_A")
+(define_insn_reservation "2_mmalua"  2
+  (and (and (eq_attr "cpu" "itanium2")
+            (eq_attr "itanium_class" "mmalua"))
+       (eq (symbol_ref "bundling_p") (const_int 0))) "2_A")
 ;; Latency time ???
 (define_insn_reservation "2_ishf"    1
   (and (and (eq_attr "cpu" "itanium2")
@@ -1016,23 +1020,24 @@
 (define_bypass  0 "2_tbit" "2_br,2_scall")
 (define_bypass  2 "2_ld" "2_ld"  "ia64_ld_address_bypass_p")
 (define_bypass  2 "2_ld" "2_st"  "ia64_st_address_bypass_p")
-(define_bypass  2 "2_ld" "2_mmmul,2_mmshf")
-(define_bypass  3 "2_ilog" "2_mmmul,2_mmshf")
-(define_bypass  3 "2_ialu" "2_mmmul,2_mmshf")
-(define_bypass  3 "2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld")
+(define_bypass  2 "2_ld" "2_mmalua,2_mmmul,2_mmshf")
+(define_bypass  3 "2_ilog" "2_mmalua,2_mmmul,2_mmshf")
+(define_bypass  3 "2_ialu" "2_mmalua,2_mmmul,2_mmshf")
+(define_bypass  3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld")
 (define_bypass  6 "2_tofr"  "2_frfr,2_stf")
 (define_bypass  7 "2_fmac"  "2_frfr,2_stf")
 
 ;; We don't use here fcmp because scall may be predicated.
 (define_bypass  0 "2_fcvtfx,2_fld,2_fmac,2_fmisc,2_frar_i,2_frar_m,\
                    2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_long_i,\
-                   2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,2_xmpy,2_xtd"
+                   2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,\
+		   2_xmpy,2_xtd"
                   "2_scall")
 
 (define_bypass  0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,\
                    2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\
-                   2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_chk_s,\
-                   2_long_i,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\
+                   2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_chk_s,2_long_i,\
+		   2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\
                    2_nop_i,2_nop_m,2_nop_x,2_rse_m,2_scall,2_sem,2_stf,2_st,\
                    2_syst_m0,2_syst_m,2_tbit,2_toar_i,2_toar_m,2_tobr,2_tofr,\
                    2_topr,2_xmpy,2_xtd,2_lfetch" "2_ignore")
@@ -1586,6 +1591,10 @@
   (and (and (eq_attr "cpu" "itanium2")
             (eq_attr "itanium_class" "ilog"))
        (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A")
+(define_insn_reservation "2b_mmalua"  2
+  (and (and (eq_attr "cpu" "itanium2")
+            (eq_attr "itanium_class" "mmalua"))
+       (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A")
 ;; Latency time ???
 (define_insn_reservation "2b_ishf"    1
   (and (and (eq_attr "cpu" "itanium2")