diff options
| author | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-06-09 17:38:06 +0000 |
|---|---|---|
| committer | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-06-09 17:38:06 +0000 |
| commit | cd8e835e48b87390255ce66bfd10cd3813de26ab (patch) | |
| tree | e97bd590a508a009e6a4942761c772456ceb0d8a /gcc/config/ia64/vect.md | |
| parent | 127d7f214d31616c6a5d979c814d8c3b5e1c1f4b (diff) | |
| download | gcc-cd8e835e48b87390255ce66bfd10cd3813de26ab.tar.gz | |
* config/ia64/ia64.c (update_set_flags): Just return for IF_THEN_ELSE.
Use SCALAR_FLOAT_MODE_P.
* config/ia64/vect.md (vcondv2sf): Remove code check on comparison.
(fselect): Rename from fpcmp; use %F.
(fpcmp): New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@100803 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/ia64/vect.md')
| -rw-r--r-- | gcc/config/ia64/vect.md | 37 |
1 files changed, 12 insertions, 25 deletions
diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md index 07e86f9f171..293707d8914 100644 --- a/gcc/config/ia64/vect.md +++ b/gcc/config/ia64/vect.md @@ -1,5 +1,5 @@ ;; IA-64 machine description for vector operations. -;; Copyright (C) 2004 +;; Copyright (C) 2004, 2005 ;; ;; This file is part of GCC. ;; @@ -873,30 +873,8 @@ { rtx x, cmp; - PUT_MODE (operands[3], V2SFmode); - switch (GET_CODE (operands[3])) - { - case EQ: - case NE: - case LT: - case LE: - case UNORDERED: - case ORDERED: - break; - - case GT: - case GE: - x = XEXP (operands[3], 0); - XEXP (operands[3], 0) = XEXP (operands[3], 1); - XEXP (operands[3], 1) = x; - PUT_CODE (operands[3], swap_condition (GET_CODE (operands[3]))); - break; - - default: - gcc_unreachable (); - } - cmp = gen_reg_rtx (V2SFmode); + PUT_MODE (operands[3], V2SFmode); emit_insn (gen_rtx_SET (VOIDmode, cmp, operands[3])); x = gen_rtx_IF_THEN_ELSE (V2SFmode, cmp, operands[1], operands[2]); @@ -906,12 +884,21 @@ (define_insn "*fpcmp" [(set (match_operand:V2SF 0 "fr_register_operand" "=f") + (match_operator:V2SF 3 "comparison_operator" + [(match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") + (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")]))] + "" + "fpcmp.%D3 %0 = %F1, %F2" + [(set_attr "itanium_class" "fmisc")]) + +(define_insn "*fselect" + [(set (match_operand:V2SF 0 "fr_register_operand" "=f") (if_then_else:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU") (match_operand:V2SF 3 "fr_reg_or_0_operand" "fU")))] "" - "fselect %0 = %2, %3, %1" + "fselect %0 = %F2, %F3, %1" [(set_attr "itanium_class" "fmisc")]) (define_expand "vec_initv2sf" |