addsub.md (addqi3): Disparage a0/a1.

* config/m32c/addsub.md (addqi3): Disparage a0/a1.
(addpsi3): Expand to include memory operands.  Remove
reload-specific splits.
* config/m32c/bitops.md (bset_qi, bset_hi, bclr_qi): New.
(andqi3_16, andhi3_16, iorqi3_16, iorhi3_16): New.
(andqi3_24, andhi3_24, iorqi3_24, iorhi3_24): New.
(andqi3, andhi3, iorqi3, iorhi3): Convert to expanders.
(shift1_qi, shift1_hi, insv): New.
* config/m32c/cond.md (cbranchqi4, cbranchhi4): Remove.
(cbranch<mode>4, stzx_16, stzx_24_<mode>, stzx_reversed,
cmp<mode>, b<code>, s<code>, s<code>_24, movqicc, movhicc,
cond_to_int): New.
* config/m32c/m32c-protos.h: Update as needed.
* config/m32c/m32c.c (m32c_reg_class_from_constraint): Don't
default the Rcr, Rcl, Raw, and Ral constraints.  Add Ra0 and Ra1.
Fail for unrecognized R* constraints.
(m32c_cannot_change_mode_class): Be more picky about pseudos.
(m32c_const_ok_for_constraint_p): Add Imb, Imw, and I00.
(m32c_extra_constraint_p2): Allow (mem (plus (plus fb int) int)).
Add Sp constraint.
(m32c_init_libfuncs): New.
(m32c_legitimate_address_p): Add debug wrapper.
(m32c_rtx_costs): New.
(m32c_address_cost): New.
(conversions): Add 'B' prefix.
(m32c_print_operand): 'h' and 'H' pick lower and upper halves of
operands, or word regnames for QI operands.  'B' prints bit
position.
(m32c_expand_setmemhi): New.
(m32c_expand_movmemhi): New.
(m32c_expand_movstr): New.
(m32c_expand_cmpstr): New.
(m32c_prepare_shift): Shift counts are limited to 16 bits at a time.
(m32c_expand_neg_mulpsi3): Handle non-ints.
(m32c_cmp_flg_0): New.
(m32c_expand_movcc): New.
(m32c_expand_insv): New.
(m32c_scc_pattern): New.
* config/m32c/m32c.h (reg classes): Add AO_REGS and A1_REGS.  Take
a0/a1 out of SIregs.
(STORE_FLAG_VALUE): New.
* config/m32c/m32c.md: Add unspecs for string moves.  Define various mode and
code macros.
(no_insn): New.
* config/m32c/mov.md: Make constraints more liberal.
(zero_extendqihi2): Optimize r0/r1 case.
* config/m32c/muldiv.md (mulpsi3): Check for intvals.
* config/m32c/predicates.md (m32c_any_operand): New.
(m32c_nonimmediate_operand): New.
(m32c_hl_operand): New.
(m32c_r3_operand): New.
(ap_operand): New.
(ma_operand): New.
(memsym_operand): New.
(memimmed_operand): New.
(a_qi_operand): New.
(m32c_eqne_operator): New.
(m32c_1bit8_operand): New.
(m32c_1bit16_operand): New.
(m32c_1mask8_operand): New.
(m32c_1mask16_operand): New.
* config/m32c/blkmov.md: New file.
* config/m32c/t-m32c (MD_FILES): Add blkmov.

From-SVN: r111859

1 files changed, 44 insertions, 45 deletions

diff --git a/gcc/config/m32c/mov.md b/gcc/config/m32c/mov.md
index c3794a3b2ed..1a6878d0e7c 100644
--- a/gcc/config/m32c/mov.md
+++ b/gcc/config/m32c/mov.md
@@ -32,9 +32,9 @@
 ;; Match push/pop before mov.b for passing char as arg,
 ;; e.g. stdlib/efgcvt.c.
 (define_insn "movqi_op"
-  [(set (match_operand:QI 0 "mra_qi_operand"
+  [(set (match_operand:QI 0 "m32c_nonimmediate_operand"
 			  "=Rqi*Rmm, <,          RqiSd*Rmm, SdSs,    Rqi*Rmm, Sd")
-	(match_operand:QI 1 "mrai_qi_operand"
+	(match_operand:QI 1 "m32c_any_operand"
 			  "iRqi*Rmm, iRqiSd*Rmm, >,         Rqi*Rmm, SdSs,    i"))]
   "m32c_mov_ok (operands, QImode)"
   "@
@@ -48,17 +48,17 @@
   )
 
 (define_expand "movqi"
-  [(set (match_operand:QI 0 "mra_qi_operand" "=RqiSd*Rmm")
-	(match_operand:QI 1 "mrai_qi_operand" "iRqiSd*Rmm"))]
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=RqiSd*Rmm")
+	(match_operand:QI 1 "general_operand" "iRqiSd*Rmm"))]
   ""
   "if (m32c_prepare_move (operands, QImode)) DONE;"
   )
 
 
 (define_insn "movhi_op"
-  [(set (match_operand:HI 0 "nonimmediate_operand"
+  [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
 			  "=Rhi*Rmm,     Sd, SdSs,   *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
-	(match_operand:HI 1 "general_operand"
+	(match_operand:HI 1 "m32c_any_operand"
 			  "iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
   "m32c_mov_ok (operands, HImode)"
   "@
@@ -75,18 +75,18 @@
   )
 
 (define_expand "movhi"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=RhiSd*Rmm")
-	(match_operand:HI 1 "general_operand" "iRhiSd*Rmm"))]
+  [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhiSd*Rmm")
+	(match_operand:HI 1 "m32c_any_operand" "iRhiSd*Rmm"))]
   ""
   "if (m32c_prepare_move (operands, HImode)) DONE;"
   )
 
 
 (define_insn "movpsi_op"
-  [(set (match_operand:PSI 0 "nonimmediate_operand"
-			   "=Raa, SdRmmRpi,  Rcl,  RpiSd*Rmm, <,       <, Rcl, Rsi*Rmm")
-	(match_operand:PSI 1 "general_operand"
-			   "sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rsi*Rmm, Rcl, >, >"))]
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand"
+			   "=Raa, SdRmmRpi,  Rcl,  RpiSd*Rmm, <,       <, Rcl, RpiRaa*Rmm")
+	(match_operand:PSI 1 "m32c_any_operand"
+			   "sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rpi*Rmm, Rcl, >, >"))]
   "TARGET_A24 && m32c_mov_ok (operands, PSImode)"
   "@
    mov.l:s\t%1,%0
@@ -104,9 +104,6 @@
 ;; The intention here is to combine the add with the move to create an
 ;; indexed move.  GCC doesn't always figure this out itself.
 
-(define_mode_macro QHSI [QI HI SI])
-(define_mode_macro HPSI [(HI "TARGET_A16") (PSI "TARGET_A24")])
-
 (define_peephole2
   [(set (match_operand:HPSI 0 "register_operand" "")
 	(plus:HPSI (match_operand:HPSI 1 "register_operand" "")
@@ -128,7 +125,7 @@
 	(plus:HPSI (match_operand:HPSI 1 "register_operand" "")
 		   (match_operand:HPSI 2 "immediate_operand" "")))
    (set (mem:QHSI (match_operand:HPSI 4 "register_operand" ""))
-	(match_operand:QHSI 3 "general_operand" ""))]
+	(match_operand:QHSI 3 "m32c_any_operand" ""))]
   "REGNO (operands[0]) == REGNO (operands[1])
    && REGNO (operands[0]) == REGNO (operands[4])
    && dead_or_set_p (peep2_next_insn (1), operands[4])
@@ -141,8 +138,8 @@
 
 ; Some PSI moves must be split.
 (define_split
-  [(set (match_operand:PSI 0 "nonimmediate_operand" "")
-	(match_operand:PSI 1 "general_operand" ""))]
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
+	(match_operand:PSI 1 "m32c_any_operand" ""))]
   "reload_completed && m32c_split_psi_p (operands)"
   [(set (match_dup 2)
 	(match_dup 3))
@@ -152,8 +149,8 @@
   )
 
 (define_expand "movpsi"
-  [(set (match_operand:PSI 0 "mras_operand" "")
-	(match_operand:PSI 1 "mrasi_operand" ""))]
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
+	(match_operand:PSI 1 "m32c_any_operand" ""))]
   ""
   "if (m32c_prepare_move (operands, PSImode)) DONE;"
   )
@@ -161,16 +158,16 @@
 
 
 (define_expand "movsi"
-  [(set (match_operand:SI 0 "mras_operand" "=RsiSd*Rmm")
-	(match_operand:SI 1 "mrasi_operand" "iRsiSd*Rmm"))]
+  [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm")
+	(match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm"))]
   ""
   "if (m32c_split_move (operands, SImode, 0)) DONE;"
   )
 
 ; All SI moves are split if TARGET_A16
 (define_insn_and_split "movsi_splittable"
-  [(set (match_operand:SI 0 "mras_operand" "=Rsi<*Rmm,RsiSd*Rmm,Ss")
-	(match_operand:SI 1 "mrasi_operand" "iRsiSd*Rmm,iRsi>*Rmm,Rsi*Rmm"))]
+  [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=Rsi<*Rmm,RsiSd*Rmm,Ss")
+	(match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm,iRsi>*Rmm,Rsi*Rmm"))]
   "TARGET_A16"
   "#"
   "TARGET_A16 && reload_completed"
@@ -182,14 +179,14 @@
 ; don't match.
 (define_insn "push_a01_l"
   [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
-	(match_operand 0 "a_operand" ""))]
+	(match_operand 0 "a_operand" "Raa"))]
   ""
   "push.l\t%0"
   )
 
 (define_insn "movsi_24"
-  [(set (match_operand:SI 0 "mras_operand"  "=Rsi*Rmm,   Sd,       RsiSd*Rmm,     <")
-	(match_operand:SI 1 "mrasi_operand" "iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm"))]
+  [(set (match_operand:SI 0 "m32c_nonimmediate_operand"  "=Rsi*Rmm,   Sd,       RsiSd*Rmm,     <")
+	(match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm"))]
   "TARGET_A24"
   "@
    mov.l\t%1,%0
@@ -199,15 +196,15 @@
   )
 
 (define_expand "movdi"
-  [(set (match_operand:DI 0 "mras_operand" "=RdiSd*Rmm")
-	(match_operand:DI 1 "mrasi_operand" "iRdiSd*Rmm"))]
+  [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=RdiSd*Rmm")
+	(match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm"))]
   ""
   "if (m32c_split_move (operands, DImode, 0)) DONE;"
   )
 
 (define_insn_and_split "movdi_splittable"
-  [(set (match_operand:DI 0 "mras_operand" "=Rdi<*Rmm,RdiSd*Rmm")
-	(match_operand:DI 1 "mrasi_operand" "iRdiSd*Rmm,iRdi>*Rmm"))]
+  [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=Rdi<*Rmm,RdiSd*Rmm")
+	(match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm,iRdi>*Rmm"))]
   ""
   "#"
   "reload_completed"
@@ -305,7 +302,7 @@
 
 ;; Rhl used here as an HI-mode Rxl
 (define_insn "extendqihi2"
-[(set (match_operand:HI 0 "mra_operand" "=RhlSd*Rmm")
+[(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhlSd*Rmm")
 	(sign_extend:HI (match_operand:QI 1 "mra_operand" "0")))]
   ""
   "exts.b\t%1"
@@ -313,7 +310,7 @@
   )
 
 (define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "r0123_operand" "=R03")
+  [(set (match_operand:SI 0 "register_operand" "=R03")
 	(sign_extend:SI (match_operand:HI 1 "r0123_operand" "0")))]
   ""
   "*
@@ -337,28 +334,30 @@
   )
 
 (define_insn "zero_extendhipsi2"
-  [(set (match_operand:PSI 0 "nonimmediate_operand" "=Raa")
-	(truncate:PSI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "Rhi"))))]
+  [(set (match_operand:PSI 0 "register_operand" "=Raa")
+	(truncate:PSI (zero_extend:SI (match_operand:HI 1 "register_operand" "R03"))))]
   ""
   "mov.w\t%1,%0"
   )
 
 (define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=RsiSd")
+  [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd")
 	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))]
   ""
   "mov.w\t#0,%H0"
   )
 
 (define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=RsiRaaSd*Rmm")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
+  [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=Rhl,RhiSd*Rmm")
+	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
   ""
-  "and.w\t#255,%0"
+  "@
+   mov.b\t#0,%H0
+   and.w\t#255,%0"
   )
 
 (define_insn "truncsipsi2_16"
-  [(set (match_operand:PSI 0 "nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
 	(truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
   "TARGET_A16"
   "@
@@ -369,15 +368,15 @@
   )
 
 (define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "mra_qi_operand" "=RqiRmmSd")
+  [(set (match_operand:QI 0 "m32c_nonimmediate_operand" "=RqiRmmSd")
 	(truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))]
   ""
   "; no-op trunc hi %1 to qi %0"
   )
 
 (define_insn "truncsipsi2_24"
-  [(set (match_operand:PSI 0              "nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm")
-	(truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))]
+  [(set (match_operand:PSI 0              "m32c_nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm")
+	(truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))]
   "TARGET_A24"
   "@
    ; no-op trunc si %1 to psi %0
@@ -387,8 +386,8 @@
   )
 
 (define_expand "truncsipsi2"
-  [(set (match_operand:PSI 0 "nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
-	(truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
+	(truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
   ""
   ""
   )