summaryrefslogtreecommitdiff
path: root/gcc/config/m68hc11/m68hc11.c
diff options
context:
space:
mode:
authorkazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4>2004-09-18 19:19:40 +0000
committerkazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4>2004-09-18 19:19:40 +0000
commita361b456a6601ea251d6fa2365ef359963fbf62e (patch)
treeb5db05c8d76e4eb55fa3eba83d2a2eac1b12bf33 /gcc/config/m68hc11/m68hc11.c
parent7d32f35df7eb0e4731ff04d04baf131ce550048d (diff)
downloadgcc-a361b456a6601ea251d6fa2365ef359963fbf62e.tar.gz
* config/darwin-c.c, config/arc/arc.c, config/arc/arc.md,
config/arm/README-interworking, config/arm/arm-cores.def, config/arm/arm.c, config/arm/arm.h, config/arm/pe.c, config/arm/vfp.md, config/c4x/c4x.c, config/c4x/c4x.h, config/cris/cris.c, config/cris/cris.h, config/fr30/fr30.c, config/fr30/fr30.h, config/fr30/fr30.md, config/frv/frv.c, config/frv/frv.md, config/i386/winnt.c, config/ia64/unwind-ia64.c, config/iq2000/iq2000.c, config/iq2000/iq2000.h, config/m68hc11/m68hc11.c, config/m68hc11/m68hc11.md, config/m68k/m68k.c, config/mcore/mcore.c, config/mips/mips.h, config/mn10300/mn10300.md, config/pa/pa.c, config/pa/pa64-regs.h, config/pdp11/pdp11.c, config/rs6000/rs6000.c, config/sh/symbian.c, config/sparc/sparc.h: Fix comment typos. Follow spelling conventions. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@87706 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/m68hc11/m68hc11.c')
-rw-r--r--gcc/config/m68hc11/m68hc11.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/m68hc11/m68hc11.c b/gcc/config/m68hc11/m68hc11.c
index 4d47a6275cf..651c642d953 100644
--- a/gcc/config/m68hc11/m68hc11.c
+++ b/gcc/config/m68hc11/m68hc11.c
@@ -850,7 +850,7 @@ m68hc11_reload_operands (rtx operands[])
/* If the offset is out of range, we have to compute the address
with a separate add instruction. We try to do with with an 8-bit
add on the A register. This is possible only if the lowest part
- of the offset (ie, big_offset % 256) is a valid constant offset
+ of the offset (i.e., big_offset % 256) is a valid constant offset
with respect to the mode. If it's not, we have to generate a
16-bit add on the D register. From: