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authorkenner <kenner@138bc75d-0d04-0410-961f-82ee72b054a4>1997-01-19 22:09:11 +0000
committerkenner <kenner@138bc75d-0d04-0410-961f-82ee72b054a4>1997-01-19 22:09:11 +0000
commit1f652457d0c868dc3702c5a711c70bd337e6cc38 (patch)
tree54af9a55850ea83d2e90e62ec3f7b6227e39b1d2 /gcc/config/m68k/m68k.md
parent4572e18f34139ac518123ac607b416ab81923e26 (diff)
downloadgcc-1f652457d0c868dc3702c5a711c70bd337e6cc38.tar.gz
Fix previous change: {add,sub}qw should be {add,sub}ql. For other uses
of {add,sub}q don't check for address register and always use {add,sub}ql. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@13523 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/m68k/m68k.md')
-rw-r--r--gcc/config/m68k/m68k.md16
1 files changed, 6 insertions, 10 deletions
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 2f0201c5ccb..2244adff18b 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -2154,21 +2154,17 @@
#ifndef NO_ADDSUB_Q
if (INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) <= 8)
- return (ADDRESS_REG_P (operands[0]) && !TARGET_5200
- ? \"addq%.w %2,%0\"
- : \"addq%.l %2,%0\");
+ return \"addq%.l %2,%0\";
if (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) >= -8)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[2]));
- return (ADDRESS_REG_P (operands[0]) && !TARGET_5200
- ? \"subq%.w %2,%0\"
- : \"subq%.l %2,%0\");
+ return \"subq%.l %2,%0\";
}
- /* On the CPU32 it is faster to use two addqw instructions to
+ /* On the CPU32 it is faster to use two addql instructions to
add a small integer (8 < N <= 16) to a register.
- Likewise for subqw. */
+ Likewise for subql. */
if (TARGET_CPU32 && REG_P (operands[0]))
{
if (INTVAL (operands[2]) > 8
@@ -2176,14 +2172,14 @@
{
operands[2] = gen_rtx (CONST_INT, VOIDmode,
INTVAL (operands[2]) - 8);
- return \"addq%.w %#8,%0\;addq%.w %2,%0\";
+ return \"addq%.l %#8,%0\;addq%.l %2,%0\";
}
if (INTVAL (operands[2]) < -8
&& INTVAL (operands[2]) >= -16)
{
operands[2] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[2]) - 8);
- return \"subq%.w %#8,%0\;subq%.w %2,%0\";
+ return \"subq%.l %#8,%0\;subq%.l %2,%0\";
}
}
#endif