h

Added -mpcrel flag, and underlying support for PC-relative addressing
on m68k. Patch is tested, and approved by Jim Wilson.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@27576 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 144 insertions, 94 deletions

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index a8dac721d99..c36e5dd3fae 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -502,7 +502,7 @@
   "
 {
   m68k_last_compare_had_fp_operands = 0;
-  if (flag_pic && symbolic_operand (operands[1], SImode))
+  if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
     {
       /* The source is an address which requires PIC relocation.
          Call legitimize_pic_address with the source, mode, and a relocation
@@ -517,8 +517,8 @@
 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
 (define_insn ""
   [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
-		 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
+        (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
+                 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
   "!TARGET_5200"
   "*
 {
@@ -580,15 +580,15 @@
 
 (define_expand "cmphi"
   [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "")
-		 (match_operand:HI 1 "general_operand" "")))]
+        (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
+                 (match_operand:HI 1 "general_src_operand" "")))]
   "!TARGET_5200"
   "m68k_last_compare_had_fp_operands = 0;")
 
 (define_insn ""
   [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
-		 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
+        (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
+                 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
   "!TARGET_5200"
   "*
 {
@@ -616,15 +616,15 @@
 
 (define_expand "cmpqi"
   [(set (cc0)
-	(compare (match_operand:QI 0 "nonimmediate_operand" "")
-		 (match_operand:QI 1 "general_operand" "")))]
+        (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
+                 (match_operand:QI 1 "general_src_operand" "")))]
   "!TARGET_5200"
   "m68k_last_compare_had_fp_operands = 0;")
 
 (define_insn ""
   [(set (cc0)
-	(compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
-		 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
+        (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
+                 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
   "!TARGET_5200"
   "*
 {
@@ -765,7 +765,7 @@
 ;; from a MEM at a constant bit position if we can't use this as a constraint.
 
 (define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
+  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
 			    (const_int 1)
 			    (minus:SI (const_int 7)
 				      (match_operand:SI 1 "general_operand" "di"))))]
@@ -948,7 +948,7 @@
   ""
   "
 {
-  if (flag_pic && symbolic_operand (operands[1], SImode))
+  if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
     {
       /* The source is an address which requires PIC relocation.
          Call legitimize_pic_address with the source, mode, and a relocation
@@ -958,6 +958,17 @@
       rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
       operands[1] = legitimize_pic_address (operands[1], SImode, temp);
     }
+  else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
+    {
+      /* Don't allow writes to memory except via a register;
+	 the m68k doesn't consider PC-relative addresses to be writable.  */
+      if (symbolic_operand (operands[0], SImode))
+	operands[0] = force_reg (SImode, XEXP (operands[0], 0));
+      else if (GET_CODE (operands[0]) == MEM
+	       && symbolic_operand (XEXP (operands[0], 0), SImode))
+	operands[0] = gen_rtx (MEM, SImode,
+			       force_reg (SImode, XEXP (operands[0], 0)));
+    }
 }")
 
 ;; General case of fullword move.  The register constraints
@@ -967,12 +978,13 @@
   ;; Notes: make sure no alternative allows g vs g.
   ;; We don't allow f-regs since fixed point cannot go in them.
   ;; We do allow y and x regs since fixed point is allowed in them.
-  [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
-	(match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
+  [(set (match_operand:SI 0 "general_operand" "=g,d,a<,y,!*x*r*m")
+        (match_operand:SI 1 "general_src_operand" "daymSKT,n,i,g,*x*r*m"))]
+
   "!TARGET_5200"
   "*
 {
-  if (which_alternative == 3)
+  if (which_alternative == 4)
     return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
   if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
     return \"fpmove%.l %x1,%x0\";
@@ -985,6 +997,19 @@
   "TARGET_5200"
   "* return output_move_simode (operands);")
 
+;; Special case of fullword move, where we need to get a non-GOT PIC
+;; reference into an address register.
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=a<")
+        (match_operand:SI 1 "pcrel_address" ""))]
+  "TARGET_PCREL"
+  "*
+{
+  if (push_operand (operands[0], SImode))
+    return \"pea %a1\";
+  return \"lea %a1,%0\";
+}")
+
 (define_expand "movhi"
   [(set (match_operand:HI 0 "general_operand" "")
 	(match_operand:HI 1 "general_operand" ""))]
@@ -993,7 +1018,7 @@
 
 (define_insn ""
   [(set (match_operand:HI 0 "general_operand" "=g")
-	(match_operand:HI 1 "general_operand" "g"))]
+        (match_operand:HI 1 "general_src_operand" "gS"))]
   "!TARGET_5200"
   "* return output_move_himode (operands);")
 
@@ -1005,55 +1030,55 @@
 
 (define_expand "movstricthi"
   [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
-	(match_operand:HI 1 "general_operand" ""))]
+        (match_operand:HI 1 "general_src_operand" ""))]
   ""
   "")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
-	(match_operand:HI 1 "general_operand" "rmn"))]
+	(match_operand:HI 1 "general_src_operand" "rmSn"))]
   "!TARGET_5200"
   "* return output_move_stricthi (operands);")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
-	(match_operand:HI 1 "general_operand" "rmn,r"))]
+	(match_operand:HI 1 "general_src_operand" "rmn,r"))]
   "TARGET_5200"
   "* return output_move_stricthi (operands);")
 
 (define_expand "movqi"
   [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
+        (match_operand:QI 1 "general_src_operand" ""))]
   ""
   "")
 
 (define_insn ""
   [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
-	(match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
+	(match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
   "!TARGET_5200"
   "* return output_move_qimode (operands);")
 
 (define_insn ""
   [(set (match_operand:QI 0 "general_operand" "=d<Q>,dm,d*a")
-	(match_operand:QI 1 "general_operand" "dmi,d<Q>,di*a"))]
+	(match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
   "TARGET_5200"
   "* return output_move_qimode (operands);")
 
 (define_expand "movstrictqi"
   [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
-	(match_operand:QI 1 "general_operand" ""))]
+        (match_operand:QI 1 "general_src_operand" ""))]
   ""
   "")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
-	(match_operand:QI 1 "general_operand" "dmn"))]
+	(match_operand:QI 1 "general_src_operand" "dmSn"))]
   "!TARGET_5200"
   "* return output_move_strictqi (operands);")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
-	(match_operand:QI 1 "general_operand" "dmn,d"))]
+	(match_operand:QI 1 "general_src_operand" "dmn,d"))]
   "TARGET_5200"
   "* return output_move_strictqi (operands);")
 
@@ -1234,6 +1259,15 @@
 	operands[1] = change_address (operands[1], XFmode,
 				      XEXP (operands[1], 0));
     }
+  if (flag_pic && TARGET_PCREL && ! reload_in_progress)
+    {
+      /* Don't allow writes to memory except via a register;
+	 the m68k doesn't consider PC-relative addresses to be writable.  */
+      if (GET_CODE (operands[0]) == MEM
+	  && symbolic_operand (XEXP (operands[0], 0), SImode))
+	operands[0] = gen_rtx (MEM, XFmode,
+			       force_reg (SImode, XEXP (operands[0], 0)));
+    }
 }")
 
 (define_insn ""
@@ -1398,7 +1432,7 @@
 (define_insn "truncsiqi2"
   [(set (match_operand:QI 0 "general_operand" "=dm,d")
 	(truncate:QI
-	 (match_operand:SI 1 "general_operand" "doJ,i")))]
+	 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
   ""
   "*
 {
@@ -1417,7 +1451,7 @@
 (define_insn "trunchiqi2"
   [(set (match_operand:QI 0 "general_operand" "=dm,d")
 	(truncate:QI
-	 (match_operand:HI 1 "general_operand" "doJ,i")))]
+	 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
   ""
   "*
 {
@@ -1445,7 +1479,7 @@
 (define_insn "truncsihi2"
   [(set (match_operand:HI 0 "general_operand" "=dm,d")
 	(truncate:HI
-	 (match_operand:SI 1 "general_operand" "roJ,i")))]
+	 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
   ""
   "*
 {
@@ -1565,7 +1599,7 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+	(zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
   "*
 {
@@ -1594,7 +1628,7 @@
 
 (define_insn ""
   [(set (match_operand:HI 0 "general_operand" "=do<>,d")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+	(zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
   "*
 {
@@ -1635,7 +1669,7 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=do<>,d")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+	(zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
   "*
 {
@@ -1688,7 +1722,7 @@
 
 (define_insn "extendqidi2"
   [(set (match_operand:DI 0 "general_operand" "=d")
-	(sign_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
+        (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
   ""
   "*
 {
@@ -1703,7 +1737,7 @@
 (define_insn "extendhidi2"
   [(set (match_operand:DI 0 "general_operand" "=d")
 	(sign_extend:DI
-	 (match_operand:HI 1 "general_operand" "rm")))]
+	 (match_operand:HI 1 "general_src_operand" "rmS")))]
   ""
   "*
 {
@@ -1765,7 +1799,7 @@
 (define_insn "extendhisi2"
   [(set (match_operand:SI 0 "general_operand" "=*d,a")
 	(sign_extend:SI
-	 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
+	 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
   ""
   "*
 {
@@ -2278,7 +2312,7 @@
 (define_expand "addsi3"
   [(set (match_operand:SI 0 "general_operand" "")
 	(plus:SI (match_operand:SI 1 "general_operand" "")
-		 (match_operand:SI 2 "general_operand" "")))]
+		 (match_operand:SI 2 "general_src_operand" "")))]
   ""
   "")
 
@@ -2287,16 +2321,18 @@
 ;; This is needed since they are not themselves reloaded,
 ;; so commutativity won't apply to them.
 (define_insn "*addsi3_internal"
-  [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
-		 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
+  [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,d,a")
+        (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
+                 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
+
+
   "! TARGET_5200"
   "* return output_addsi3 (operands);")
 
 (define_insn "*addsi3_5200"
   [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
 	(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
-		 (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
+		 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
   "TARGET_5200"
   "* return output_addsi3 (operands);")
 
@@ -2304,14 +2340,14 @@
   [(set (match_operand:SI 0 "general_operand" "=a")
 	(plus:SI (match_operand:SI 1 "general_operand" "0")
 		 (sign_extend:SI
-		  (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
+		  (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
   "!TARGET_5200"
   "add%.w %2,%0")
 
 (define_insn "addhi3"
   [(set (match_operand:HI 0 "general_operand" "=m,r")
 	(plus:HI (match_operand:HI 1 "general_operand" "%0,0")
-		 (match_operand:HI 2 "general_operand" "dn,rmn")))]
+		 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
   "!TARGET_5200"
   "*
 {
@@ -2373,7 +2409,7 @@
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
 	(plus:HI (match_dup 0)
-		 (match_operand:HI 1 "general_operand" "dn,rmn")))]
+		 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
   "!TARGET_5200"
   "*
 {
@@ -2428,7 +2464,7 @@
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
+	(plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
 		 (match_dup 0)))]
   "!TARGET_5200"
   "*
@@ -2485,7 +2521,7 @@
 (define_insn "addqi3"
   [(set (match_operand:QI 0 "general_operand" "=m,d")
 	(plus:QI (match_operand:QI 1 "general_operand" "%0,0")
-		 (match_operand:QI 2 "general_operand" "dn,dmn")))]
+		 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "*
 {
@@ -2511,7 +2547,7 @@
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
 	(plus:QI (match_dup 0)
-		 (match_operand:QI 1 "general_operand" "dn,dmn")))]
+		 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "*
 {
@@ -2536,7 +2572,7 @@
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
+	(plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
 		 (match_dup 0)))]
   "!TARGET_5200"
   "*
@@ -2802,9 +2838,9 @@
 } ")
 
 (define_insn "subsi3"
-  [(set (match_operand:SI 0 "general_operand" "=m,r")
-	(minus:SI (match_operand:SI 1 "general_operand" "0,0")
-		  (match_operand:SI 2 "general_operand" "ds,mrs")))]
+  [(set (match_operand:SI 0 "general_operand" "=m,d,a")
+	(minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
+		  (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
   ""
   "sub%.l %2,%0")
 
@@ -2812,35 +2848,35 @@
   [(set (match_operand:SI 0 "general_operand" "=a")
 	(minus:SI (match_operand:SI 1 "general_operand" "0")
 		  (sign_extend:SI
-		   (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
+		   (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
   "!TARGET_5200"
   "sub%.w %2,%0")
 
 (define_insn "subhi3"
   [(set (match_operand:HI 0 "general_operand" "=m,r")
 	(minus:HI (match_operand:HI 1 "general_operand" "0,0")
-		  (match_operand:HI 2 "general_operand" "dn,rmn")))]
+		  (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
   "!TARGET_5200"
   "sub%.w %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
 	(minus:HI (match_dup 0)
-		  (match_operand:HI 1 "general_operand" "dn,rmn")))]
+		  (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
   "!TARGET_5200"
   "sub%.w %1,%0")
 
 (define_insn "subqi3"
   [(set (match_operand:QI 0 "general_operand" "=m,d")
 	(minus:QI (match_operand:QI 1 "general_operand" "0,0")
-		  (match_operand:QI 2 "general_operand" "dn,dmn")))]
+		  (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "sub%.b %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
 	(minus:QI (match_dup 0)
-		  (match_operand:QI 1 "general_operand" "dn,dmn")))]
+		  (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "sub%.b %1,%0")
 
@@ -2961,7 +2997,7 @@
 (define_insn "mulhi3"
   [(set (match_operand:HI 0 "general_operand" "=d")
 	(mult:HI (match_operand:HI 1 "general_operand" "%0")
-		 (match_operand:HI 2 "general_operand" "dmn")))]
+		 (match_operand:HI 2 "general_src_operand" "dmSn")))]
   ""
   "*
 {
@@ -2977,7 +3013,7 @@
 	(mult:SI (sign_extend:SI
 		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
 		 (sign_extend:SI
-		  (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
+		  (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
   ""
   "*
 {
@@ -3013,7 +3049,8 @@
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=d")
 	(mult:SI (match_operand:SI 1 "general_operand" "%0")
-		 (match_operand:SI 2 "general_operand" "dmsK")))]
+                 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
+
   "TARGET_68020"
   "muls%.l %2,%0")
 
@@ -3029,7 +3066,7 @@
 	(mult:SI (zero_extend:SI
 		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
 		 (zero_extend:SI
-		  (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
+		  (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
   ""
   "*
 {
@@ -3519,7 +3556,7 @@
 (define_insn "divmodsi4"
   [(set (match_operand:SI 0 "general_operand" "=d")
 	(div:SI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:SI 2 "general_operand" "dmsK")))
+		(match_operand:SI 2 "general_src_operand" "dmSTK")))
    (set (match_operand:SI 3 "general_operand" "=d")
 	(mod:SI (match_dup 1) (match_dup 2)))]
   "TARGET_68020 && !TARGET_5200"
@@ -3534,7 +3571,7 @@
 (define_insn "udivmodsi4"
   [(set (match_operand:SI 0 "general_operand" "=d")
 	(udiv:SI (match_operand:SI 1 "general_operand" "0")
-		 (match_operand:SI 2 "general_operand" "dmsK")))
+		 (match_operand:SI 2 "general_src_operand" "dmSTK")))
    (set (match_operand:SI 3 "general_operand" "=d")
 	(umod:SI (match_dup 1) (match_dup 2)))]
   "TARGET_68020 && !TARGET_5200"
@@ -3549,7 +3586,7 @@
 (define_insn "divmodhi4"
   [(set (match_operand:HI 0 "general_operand" "=d")
 	(div:HI (match_operand:HI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "dmsK")))
+		(match_operand:HI 2 "general_src_operand" "dmSKT")))
    (set (match_operand:HI 3 "general_operand" "=d")
 	(mod:HI (match_dup 1) (match_dup 2)))]
   "!TARGET_5200"
@@ -3572,7 +3609,7 @@
 (define_insn "udivmodhi4"
   [(set (match_operand:HI 0 "general_operand" "=d")
 	(udiv:HI (match_operand:HI 1 "general_operand" "0")
-		 (match_operand:HI 2 "general_operand" "dmsK")))
+		 (match_operand:HI 2 "general_src_operand" "dmSKT")))
    (set (match_operand:HI 3 "general_operand" "=d")
 	(umod:HI (match_dup 1) (match_dup 2)))]
   "!TARGET_5200"
@@ -3675,16 +3712,16 @@
 ;; can't allocate pseudos into it.
 
 (define_expand "andsi3"
-  [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
-	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "dKs,dmMs")))]
+  [(set (match_operand:SI 0 "not_sp_operand" "")
+	(and:SI (match_operand:SI 1 "general_operand" "")
+		(match_operand:SI 2 "general_src_operand" "")))]
   ""
   "")
 
 (define_insn "andsi3_internal"
   [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
 	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "dKs,dmMs")))]
+		(match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
   "!TARGET_5200"
   "*
 {
@@ -3694,27 +3731,27 @@
 (define_insn "andsi3_5200"
   [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
 	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "d,dmsK")))]
+		(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
   "TARGET_5200"
   "and%.l %2,%0")
 
 (define_insn "andhi3"
   [(set (match_operand:HI 0 "general_operand" "=m,d")
 	(and:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "dn,dmn")))]
+		(match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "and%.w %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
 	(and:HI (match_dup 0)
-		(match_operand:HI 1 "general_operand" "dn,dmn")))]
+		(match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "and%.w %1,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
+	(and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
 		(match_dup 0)))]
   "!TARGET_5200"
   "and%.w %1,%0")
@@ -3722,20 +3759,20 @@
 (define_insn "andqi3"
   [(set (match_operand:QI 0 "general_operand" "=m,d")
 	(and:QI (match_operand:QI 1 "general_operand" "%0,0")
-		(match_operand:QI 2 "general_operand" "dn,dmn")))]
+		(match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "and%.b %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
 	(and:QI (match_dup 0)
-		(match_operand:QI 1 "general_operand" "dn,dmn")))]
+		(match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "and%.b %1,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
+	(and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
 		(match_dup 0)))]
   "!TARGET_5200"
   "and%.b %1,%0")
@@ -3850,14 +3887,14 @@
 (define_expand "iorsi3"
   [(set (match_operand:SI 0 "general_operand" "")
 	(ior:SI (match_operand:SI 1 "general_operand" "")
-		(match_operand:SI 2 "general_operand" "")))]
+		(match_operand:SI 2 "general_src_operand" "")))]
   ""
   "")
 
 (define_insn "iorsi3_internal"
   [(set (match_operand:SI 0 "general_operand" "=m,d")
 	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "dKs,dmMs")))]
+                (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
   "! TARGET_5200"
   "*
 {
@@ -3867,27 +3904,27 @@
 (define_insn "iorsi3_5200"
   [(set (match_operand:SI 0 "general_operand" "=m,d")
 	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "d,dmsK")))]
+		(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
   "TARGET_5200"
   "or%.l %2,%0")
 
 (define_insn "iorhi3"
   [(set (match_operand:HI 0 "general_operand" "=m,d")
 	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "dn,dmn")))]
+		(match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "or%.w %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
 	(ior:HI (match_dup 0)
-		(match_operand:HI 1 "general_operand" "dn,dmn")))]
+		(match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "or%.w %1,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
+	(ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
 		(match_dup 0)))]
   "!TARGET_5200"
   "or%.w %1,%0")
@@ -3895,20 +3932,20 @@
 (define_insn "iorqi3"
   [(set (match_operand:QI 0 "general_operand" "=m,d")
 	(ior:QI (match_operand:QI 1 "general_operand" "%0,0")
-		(match_operand:QI 2 "general_operand" "dn,dmn")))]
+                (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "or%.b %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
 	(ior:QI (match_dup 0)
-		(match_operand:QI 1 "general_operand" "dn,dmn")))]
+                (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
   "!TARGET_5200"
   "or%.b %1,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
+        (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
 		(match_dup 0)))]
   "!TARGET_5200"
   "or%.b %1,%0")
@@ -4046,7 +4083,8 @@
 (define_insn "xorsi3_internal"
   [(set (match_operand:SI 0 "general_operand" "=do,m")
 	(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "di,dKs")))]
+                (match_operand:SI 2 "general_operand" "di,dKT")))]
+
   "!TARGET_5200"
   "*
 {
@@ -5267,7 +5305,7 @@
   [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
 			 (const_int 32)
 			 (match_operand:SI 2 "const_int_operand" "n"))
-	(match_operand:SI 3 "general_operand" "rmi"))]
+	(match_operand:SI 3 "general_src_operand" "rmSi"))]
   "TARGET_68020 && TARGET_BITFIELD
    && (INTVAL (operands[2]) % 8) == 0
    && ! mode_dependent_address_p (XEXP (operands[0], 0))"
@@ -5318,7 +5356,7 @@
 ;
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=rm")
-	(zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
+	(zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
 			 (const_int 32)
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
@@ -5372,7 +5410,7 @@
 ;
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=rm")
-	(sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
+	(sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
 			 (const_int 32)
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
@@ -6823,21 +6861,28 @@
   "*
   if (GET_CODE (operands[0]) == MEM
       && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
+    {
+      if (TARGET_PCREL) return \"bsr.l %o0\";
 #ifdef MOTOROLA
 #ifdef HPUX_ASM
-    return \"bsr.l %0\";
+      return \"bsr.l %0\";
 #else
 #ifdef USE_GAS
-    return \"bsr.l %0@PLTPC\";
+      return \"bsr.l %0@PLTPC\";
 #else
-    return \"bsr %0@PLTPC\";
+      return \"bsr %0@PLTPC\";
 #endif
 #endif
 #else
-    /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
-       GAS just plain ignores it.  */
-    return \"jbsr %0,a1\";
+#ifdef USE_GAS
+      return \"bsr.l %0\";
+#else
+      /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
+	 GAS just plain ignores it.  FIXME: not anymore, gas doesnt!  */
+      return \"jbsr %0,a1\";
 #endif
+#endif
+    }
   return \"jsr %0\";
 ")
 
@@ -6887,6 +6932,7 @@
   if (GET_CODE (operands[1]) == MEM
       && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
     {
+      if (TARGET_PCREL) return \"bsr.l %o1\";
 #ifdef MOTOROLA
 #ifdef HPUX_ASM
       return \"bsr.l %1\";
@@ -6898,10 +6944,14 @@
 #endif
 #endif
 #else
+#ifdef USE_GAS
+      return \"bsr.l %1\";
+#else
       /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
-         GAS just plain ignores it.  */
+         GAS just plain ignores it.  FIXME: Not anymore, gas doesnt!  */
       return \"jbsr %1,a1\";
 #endif
+#endif
     }
   return \"jsr %1\";
 ")