diff options
| author | dj <dj@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-07-08 04:19:16 +0000 |
|---|---|---|
| committer | dj <dj@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-07-08 04:19:16 +0000 |
| commit | aecef6a27b8a9f1bc43829e07fc186bc7d08465d (patch) | |
| tree | 5f0c76d91cdd483afadd83438c6359c91840f064 /gcc/config/mep/intrinsics.md | |
| parent | d9479d0bf68c0ca6280a872ff85e9b5d81f85ac8 (diff) | |
| download | gcc-aecef6a27b8a9f1bc43829e07fc186bc7d08465d.tar.gz | |
* config/mep/mep-ivc2.cpu (cpmovtocsar0_C3, cpmovtocsar1_C3,
cpmovtocc_C3, cpmovtocsar0_P0S_P1, cpmovtocsar1_P0S_P1,
cpmovtocc_P0S_P1): Mark volatile. Note which registers are
written to.
* config/mep/intrinsics.md: Regenerated.
* config/mep/mep.c (mep_interrupt_saved_reg): Save IVC2 control
registers when asm() or calls are detected.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@149361 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mep/intrinsics.md')
| -rw-r--r-- | gcc/config/mep/intrinsics.md | 42 |
1 files changed, 24 insertions, 18 deletions
diff --git a/gcc/config/mep/intrinsics.md b/gcc/config/mep/intrinsics.md index 76a19c92aab..44343d3b706 100644 --- a/gcc/config/mep/intrinsics.md +++ b/gcc/config/mep/intrinsics.md @@ -15862,9 +15862,10 @@ (define_insn "cgen_intrinsic_cpmovtocc_C3" - [(unspec_volatile [ - (match_operand:DI 0 "general_operand" "x") - ] 3378)] + [(set (reg:SI 81) + (unspec_volatile:SI [ + (match_operand:DI 0 "general_operand" "x") + ] 3378))] "CGEN_ENABLE_INSN_P (574)" "cpmovtocc\\t%0" [(set_attr "may_trap" "no") @@ -15876,9 +15877,10 @@ (define_insn "cgen_intrinsic_cpmovtocc_P0S_P1" - [(unspec_volatile [ - (match_operand:DI 0 "general_operand" "x") - ] 3378)] + [(set (reg:SI 81) + (unspec_volatile:SI [ + (match_operand:DI 0 "general_operand" "x") + ] 3378))] "CGEN_ENABLE_INSN_P (575)" "cpmovtocc\\t%0" [(set_attr "may_trap" "no") @@ -15890,9 +15892,10 @@ (define_insn "cgen_intrinsic_cpmovtocsar1_C3" - [(unspec_volatile [ - (match_operand:DI 0 "general_operand" "x") - ] 3380)] + [(set (reg:SI 95) + (unspec_volatile:SI [ + (match_operand:DI 0 "general_operand" "x") + ] 3380))] "CGEN_ENABLE_INSN_P (576)" "cpmovtocsar1\\t%0" [(set_attr "may_trap" "no") @@ -15904,9 +15907,10 @@ (define_insn "cgen_intrinsic_cpmovtocsar1_P0S_P1" - [(unspec_volatile [ - (match_operand:DI 0 "general_operand" "x") - ] 3380)] + [(set (reg:SI 95) + (unspec_volatile:SI [ + (match_operand:DI 0 "general_operand" "x") + ] 3380))] "CGEN_ENABLE_INSN_P (577)" "cpmovtocsar1\\t%0" [(set_attr "may_trap" "no") @@ -15918,9 +15922,10 @@ (define_insn "cgen_intrinsic_cpmovtocsar0_C3" - [(unspec_volatile [ - (match_operand:DI 0 "general_operand" "x") - ] 3382)] + [(set (reg:SI 80) + (unspec_volatile:SI [ + (match_operand:DI 0 "general_operand" "x") + ] 3382))] "CGEN_ENABLE_INSN_P (578)" "cpmovtocsar0\\t%0" [(set_attr "may_trap" "no") @@ -15932,9 +15937,10 @@ (define_insn "cgen_intrinsic_cpmovtocsar0_P0S_P1" - [(unspec_volatile [ - (match_operand:DI 0 "general_operand" "x") - ] 3382)] + [(set (reg:SI 80) + (unspec_volatile:SI [ + (match_operand:DI 0 "general_operand" "x") + ] 3382))] "CGEN_ENABLE_INSN_P (579)" "cpmovtocsar0\\t%0" [(set_attr "may_trap" "no") |