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author | clm <clm@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-03-25 13:53:53 +0000 |
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committer | clm <clm@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-03-25 13:53:53 +0000 |
commit | 087a99ba8749638f86c111f776ed326b3fbd97c0 (patch) | |
tree | a58356884d6e5da403cae2b4a8be4c4fa640b7d7 /gcc/config/mips/constraints.md | |
parent | 6cf594a49ae949e83f876108740a8d7c9cac9a43 (diff) | |
download | gcc-087a99ba8749638f86c111f776ed326b3fbd97c0.tar.gz |
2013-03-25 Catherine Moore <clm@codesourcery.com>
* config/mips/constraints.md (u, Udb7 Uead, Uean, Uesp, Uib3,
Uuw6, Usb4, ZS, ZT, ZU, ZV, ZW): New constraints.
* config/mip/predicates.md (lwsp_swsp_operand,
lw16_sw16_operand, lhu16_sh16_operand, lbu16_operand,
sb16_operand, db4_operand, db7_operand, ib3_operand,
sb4_operand, ub4_operand, uh4_operand, uw4_operand,
uw5_operand, uw6_operand, addiur2_operand, addiusp_operand,
andi16_operand): New predicates.
* config/mips/mips.md (compression): New attribute.
(enabled): New attribute.
(length): Consider compression in computing length.
(shift_compression): New code attribute.
(*add<mode>3): New operands. Record compression.
(sub<mode>3): Likewise.
(one_cmpl<mode>2): Likewise.
(*and<mode>3): Likewise.
(*ior<mode>3): Likewise.
(unnamed pattern for xor): Likewise.
(*zero_extend<SHORT:mode><GPR:mode>2): Likewise.
(*<optab><mode>3): Likewise.
(*mov<mode>_internal: Likewise.
* config/mips/mips-protos.h (mips_signed_immediate_p): New.
(mips_unsigned_immediate_p): New.
(umips_lwsp_swsp_address_p): New.
(m16_based_address_p): New.
* config/mips/mips-protos.h (mips_signed_immediate_p): New prototype.
(mips_unsigned_immediate_p): New prototype.
(lwsp_swsp_address_p): New prototype.
(m16_based_address_p): New prototype.
* config/mips/mips.c (mips_unsigned_immediate_p): New function.
(mips_signed_immediate_p): New function.
(m16_based_address_p): New function.
(lwsp_swsp_address_p): New function.
(mips_print_operand_punctuation): Recognize short delay slot insns
for microMIPS.add<mode>3"
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@197042 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mips/constraints.md')
-rw-r--r-- | gcc/config/mips/constraints.md | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md index 773ef3a71e6..e73c440e1f4 100644 --- a/gcc/config/mips/constraints.md +++ b/gcc/config/mips/constraints.md @@ -43,6 +43,9 @@ (define_register_constraint "b" "ALL_REGS" "@internal") +(define_register_constraint "u" "M16_REGS" + "@internal") + ;; MIPS16 code always calls through a MIPS16 register; see mips_emit_call_insn ;; for details. (define_register_constraint "c" "TARGET_MIPS16 ? M16_REGS @@ -170,6 +173,41 @@ (and (match_operand 0 "call_insn_operand") (match_test "CONSTANT_P (op)"))) +(define_constraint "Udb7" + "@internal + A decremented unsigned constant of 7 bits." + (match_operand 0 "db7_operand")) + +(define_constraint "Uead" + "@internal + A microMIPS encoded ADDIUR2 immediate operand." + (match_operand 0 "addiur2_operand")) + +(define_constraint "Uean" + "@internal + A microMIPS encoded ANDI operand." + (match_operand 0 "andi16_operand")) + +(define_constraint "Uesp" + "@internal + A microMIPS encoded ADDIUSP operand." + (match_operand 0 "addiusp_operand")) + +(define_constraint "Uib3" + "@internal + An unsigned, incremented constant of 3 bits." + (match_operand 0 "ib3_operand")) + +(define_constraint "Uuw6" + "@internal + An unsigned constant of 6 bits, shifted left two places." + (match_operand 0 "uw6_operand")) + +(define_constraint "Usb4" + "@internal + A signed constant of 4 bits." + (match_operand 0 "sb4_operand")) + (define_memory_constraint "W" "@internal A memory address based on a member of @code{BASE_REG_CLASS}. This is @@ -257,3 +295,34 @@ "@internal An address valid for loading/storing register exclusive" (match_operand 0 "mem_noofs_operand")) + +(define_memory_constraint "ZS" + "@internal + A microMIPS memory operand for use with the LWSP/SWSP insns." + (and (match_code "mem") + (match_operand 0 "lwsp_swsp_operand"))) + +(define_memory_constraint "ZT" + "@internal + A microMIPS memory operand for use with the LW16/SW16 insns." + (and (match_code "mem") + (match_operand 0 "lw16_sw16_operand"))) + +(define_memory_constraint "ZU" + "@internal + A microMIPS memory operand for use with the LHU16/SH16 insns." + (and (match_code "mem") + (match_operand 0 "lhu16_sh16_operand"))) + +(define_memory_constraint "ZV" + "@internal + A microMIPS memory operand for use with the SB16 insn." + (and (match_code "mem") + (match_operand 0 "sb16_operand"))) + +(define_memory_constraint "ZW" + "@internal + A microMIPS memory operand for use with the LBU16 insn." + (and (match_code "mem") + (match_operand 0 "lbu16_operand"))) + |