diff options
| author | gavin <gavin@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-11-23 19:18:48 +0000 |
|---|---|---|
| committer | gavin <gavin@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-11-23 19:18:48 +0000 |
| commit | 2cec2f388d566cc2c8134169ced6b6ac77375eae (patch) | |
| tree | e157941225513aa19f4d86f264dc0438739ccb7b /gcc/config/mips/mips.h | |
| parent | 2db59d96e87429b5ba315bb2e906e9ca521255b4 (diff) | |
| download | gcc-2cec2f388d566cc2c8134169ced6b6ac77375eae.tar.gz | |
* config/mips/mips.h (ISA_HAS_FP4,ISA_HAS_CONDMOVE,ISA_HAS_8CC): Split
the second two from the first.
(CONDITIONAL_REGISTER_USAGE): Use ISA_HAS_8CC rather than ISA_HAS_FP4.
* config/mips/mips.md (movcc,reload_incc,reload_outcc,
conditional move): Use ISA_HAS_CONDMOVE or ISA_HAS_8CC rather than
ISA_HAS_FP4.
* config/mips/mips.c (mips_move_1word,gen_conditional_branch,
override_options): Use ISA_HAS_CONDMOVE or ISA_HAS_8CC rather than
ISA_HAS_FP4.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@30643 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 1d0f1a8841d..6768a52bc8c 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -566,16 +566,29 @@ extern void sbss_section PARAMS ((void)); #define HAVE_SQRT_P() (mips_isa != 1) /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */ -#define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 || mips_isa == 64) +#define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \ + ) /* ISA has branch likely instructions (eg. mips2). */ #define ISA_HAS_BRANCHLIKELY (mips_isa != 1) -/* ISA has the FP instructions introduced in mips4. */ -#define ISA_HAS_FP4 (mips_isa == 4) +/* ISA has the conditional move instructions introduced in mips4. */ +#define ISA_HAS_CONDMOVE (mips_isa == 4 \ + ) + +/* ISA has the mips4 FP condition code instructions: FP-compare to CC, + branch on CC, and move (both FP and non-FP) on CC. */ +#define ISA_HAS_8CC (mips_isa == 4 \ + ) + + +/* This is a catch all for the other new mips4 instructions: indexed load and + indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions, + and the FP recip and recip sqrt instructions */ +#define ISA_HAS_FP4 (mips_isa == 4 \ + ) + -/* ISA has the non-FP conditional move instructions introduced in mips4. */ -#define ISA_HAS_CONDMOVE (mips_isa == 4) /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit @@ -645,7 +658,7 @@ do \ for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \ fixed_regs[regno] = call_used_regs[regno] = 1; \ } \ - else if (! ISA_HAS_FP4) \ + else if (! ISA_HAS_8CC) \ { \ int regno; \ \ |