diff options
| author | pinskia <pinskia@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-08-13 15:34:00 +0000 |
|---|---|---|
| committer | pinskia <pinskia@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-08-13 15:34:00 +0000 |
| commit | 33f88b1c70435e9803c2dbeffc56522f23484f57 (patch) | |
| tree | 878c3b36634b01083dbdab85167d3a3f2f7de154 /gcc/config/mips/sb1.md | |
| parent | 8833a11bdb254fed3c34d1c00c3a4e1e74ace31e (diff) | |
| download | gcc-33f88b1c70435e9803c2dbeffc56522f23484f57.tar.gz | |
2004-08-12 Andrew Pinski <pinskia@physics.uc.edu>
* config/darwin-c.c (find_subframework_file): Fix spelling of cannot.
* config/libgloss.h: Likewise.
* config/arm/arm.c (arm_gen_load_multiple): Likewise.
* c4x/c4x-modes.def: Likewise.
* config/c4x/c4x.c (c4x_hard_regno_rename_ok): Likewise.
(c4x_rptb_nop_p): Likewise.
(c4x_rptb_valid_p): Likewise.
(c4x_rptb_insert): Likewise.
(c4x_address_conflict): Likewise.
* config/c4x/c4x.md: Likewise.
* config/frv/frv.md: Likewise.
* config/i386/athlon.md: Likewise.
* config/i386/i386.md: Likewise.
* config/i386/predicates.md: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/itanium1.md: Likewise.
* config/ia64/itanium2.md: Likewise.
* config/iq2000/iq2000.md: Likewise.
* config/mcore/mcore.c: Likewise.
* config/mips/mips.c: Likewise.
* config/mips/r3900.h: Likewise.
* config/mips/sb1.md: Likewise.
* config/pa/milli64.S: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/pa.h: Likewise.
* config/rs6000/8540.md: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@85944 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mips/sb1.md')
| -rw-r--r-- | gcc/config/mips/sb1.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md index 41cebedce4f..aff645baffa 100644 --- a/gcc/config/mips/sb1.md +++ b/gcc/config/mips/sb1.md @@ -207,7 +207,7 @@ ;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding ;; store data), otherwise a latency of 1 cycle. -;; ??? We can not handle latencies properly for simple alu instructions +;; ??? We cannot handle latencies properly for simple alu instructions ;; within the DFA pipeline model. Latencies can be defined only from one ;; insn reservation to another. We can't make them depend on which function ;; unit was used. This isn't a DFA flaw. There is a conflict here, as we |