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author | sayle <sayle@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-08-10 17:43:02 +0000 |
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committer | sayle <sayle@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-08-10 17:43:02 +0000 |
commit | 10d0c4c6702e026c1a0f0d9c0438cae32fec1084 (patch) | |
tree | 6c1c247cb4ccfbb4b6e56f40f779cebfd2c2b759 /gcc/config/mips | |
parent | 4c44712e3cb956d61e7a793548fb1a8f85f5ad68 (diff) | |
download | gcc-10d0c4c6702e026c1a0f0d9c0438cae32fec1084.tar.gz |
* config/mips/mips.md: New reciprocal square root patterns that
match sqrt(1.0/x) in addition to the existing 1.0/sqrt(x) insns.
* gcc.dg/mips-rsqrt-1.c: New test case.
* gcc.dg/mips-rsqrt-2.c: New test case.
* gcc.dg/mips-rsqrt-3.c: New test case.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@85759 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mips')
-rw-r--r-- | gcc/config/mips/mips.md | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 7c6771dd749..ac4c4b9473e 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -2203,6 +2203,46 @@ (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0)) (const_int 8) (const_int 4)))]) + +;; This pattern works around the early SB-1 rev2 core "F1" erratum (see +;; "divdf3" comment for details). +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (sqrt:DF (div:DF (match_operand:DF 1 "const_float_1_operand" "") + (match_operand:DF 2 "register_operand" "f"))))] + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations" +{ + if (TARGET_FIX_SB1) + return "rsqrt.d\t%0,%2\;mov.d\t%0,%0"; + else + return "rsqrt.d\t%0,%2"; +} + [(set_attr "type" "frsqrt") + (set_attr "mode" "DF") + (set (attr "length") + (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0)) + (const_int 8) + (const_int 4)))]) + +;; This pattern works around the early SB-1 rev2 core "F1" erratum (see +;; "divdf3" comment for details). +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (sqrt:SF (div:SF (match_operand:SF 1 "const_float_1_operand" "") + (match_operand:SF 2 "register_operand" "f"))))] + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations" +{ + if (TARGET_FIX_SB1) + return "rsqrt.s\t%0,%2\;mov.s\t%0,%0"; + else + return "rsqrt.s\t%0,%2"; +} + [(set_attr "type" "frsqrt") + (set_attr "mode" "SF") + (set (attr "length") + (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0)) + (const_int 8) + (const_int 4)))]) ;; ;; .................... |