2016-02-10 Basile Starynkevitch <basile@starynkevitch.net>

	{{merging with more of GCC 6, using
	svn merge -r225091:227000 ^/trunk }}
 



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@233280 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 39 insertions, 33 deletions

diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 244eb8d51cb..d9ad9100f99 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -303,6 +303,7 @@ extern const char *mips_output_sync_loop (rtx_insn *, rtx *);
 extern unsigned int mips_sync_loop_insns (rtx_insn *, rtx *);
 extern const char *mips_output_division (const char *, rtx *);
 extern const char *mips_output_probe_stack_range (rtx, rtx);
+extern bool mips_hard_regno_rename_ok (unsigned int, unsigned int);
 extern unsigned int mips_hard_regno_nregs (int, machine_mode);
 extern bool mips_linked_madd_p (rtx_insn *, rtx_insn *);
 extern bool mips_store_data_bypass_p (rtx_insn *, rtx_insn *);
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index bf0f84f5356..401d73bfeaa 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -1255,32 +1255,6 @@ static const struct mips_rtx_cost_data
 		    2,            /* branch_cost */
 		    4             /* memory_latency */
   },
-  { /* W32 */
-    COSTS_N_INSNS (4),            /* fp_add */
-    COSTS_N_INSNS (4),            /* fp_mult_sf */
-    COSTS_N_INSNS (5),            /* fp_mult_df */
-    COSTS_N_INSNS (17),           /* fp_div_sf */
-    COSTS_N_INSNS (32),           /* fp_div_df */
-    COSTS_N_INSNS (5),            /* int_mult_si */
-    COSTS_N_INSNS (5),            /* int_mult_di */
-    COSTS_N_INSNS (41),           /* int_div_si */
-    COSTS_N_INSNS (41),           /* int_div_di */
-		     1,           /* branch_cost */
-		     4            /* memory_latency */
-  },
-  { /* W64 */
-    COSTS_N_INSNS (4),            /* fp_add */
-    COSTS_N_INSNS (4),            /* fp_mult_sf */
-    COSTS_N_INSNS (5),            /* fp_mult_df */
-    COSTS_N_INSNS (17),           /* fp_div_sf */
-    COSTS_N_INSNS (32),           /* fp_div_df */
-    COSTS_N_INSNS (5),            /* int_mult_si */
-    COSTS_N_INSNS (5),            /* int_mult_di */
-    COSTS_N_INSNS (41),           /* int_div_si */
-    COSTS_N_INSNS (41),           /* int_div_di */
-		     1,           /* branch_cost */
-		     4            /* memory_latency */
-  },
   { /* M5100 */
     COSTS_N_INSNS (4),            /* fp_add */
     COSTS_N_INSNS (4),            /* fp_mult_sf */
@@ -12307,6 +12281,33 @@ mips_hard_regno_mode_ok_p (unsigned int regno, machine_mode mode)
   return false;
 }
 
+/* Return nonzero if register OLD_REG can be renamed to register NEW_REG.  */
+
+bool
+mips_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
+			   unsigned int new_reg)
+{
+  /* Interrupt functions can only use registers that have already been
+     saved by the prologue, even if they would normally be call-clobbered.  */
+  if (cfun->machine->interrupt_handler_p && !df_regs_ever_live_p (new_reg))
+    return false;
+
+  return true;
+}
+
+/* Return nonzero if register REGNO can be used as a scratch register
+   in peephole2.  */
+
+bool
+mips_hard_regno_scratch_ok (unsigned int regno)
+{
+  /* See mips_hard_regno_rename_ok.  */
+  if (cfun->machine->interrupt_handler_p && !df_regs_ever_live_p (regno))
+    return false;
+
+  return true;
+}
+
 /* Implement HARD_REGNO_NREGS.  */
 
 unsigned int
@@ -13615,7 +13616,7 @@ mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
   if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
     return false;
 
-  return !store_data_bypass_p (out_insn, in_insn);
+  return store_data_bypass_p (out_insn, in_insn);
 }
 
 
@@ -19853,6 +19854,9 @@ mips_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class)
 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class
 
+#undef TARGET_HARD_REGNO_SCRATCH_OK
+#define TARGET_HARD_REGNO_SCRATCH_OK mips_hard_regno_scratch_ok
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-mips.h"
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index d17a833c743..da1de011fc9 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1876,6 +1876,9 @@ FP_ASM_SPEC "\
 #define HARD_REGNO_MODE_OK(REGNO, MODE)					\
   mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
 
+#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG)				\
+  mips_hard_regno_rename_ok (OLD_REG, NEW_REG)
+
 /* Select a register mode required for caller save of hard regno REGNO.  */
 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
   mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
@@ -3177,5 +3180,5 @@ extern GTY(()) struct target_globals *micromips_globals;
    performance can be degraded for those targets.  Hence, do not bond for
    micromips or fix_24k.  */
 #define ENABLE_LD_ST_PAIRS \
-  (TARGET_LOAD_STORE_PAIRS && TUNE_P5600 \
+  (TARGET_LOAD_STORE_PAIRS && (TUNE_P5600 || TUNE_I6400) \
    && !TARGET_MICROMIPS && !TARGET_FIX_24K)
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 2954a12702b..a0079d5c974 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -67,8 +67,6 @@
   xlr
   xlp
   p5600
-  w32
-  w64
   m5100
   i6400
 ])
diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md
index 19b9b324653..e8d1f1b2da8 100644
--- a/gcc/config/mips/sb1.md
+++ b/gcc/config/mips/sb1.md
@@ -216,7 +216,7 @@
   "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
    ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
   "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
-  "mips_store_data_bypass_p")
+  "!mips_store_data_bypass_p")
 
 ;; On SB-1, simple alu instructions can execute on the LS1 unit.
 
@@ -289,7 +289,7 @@
 (define_bypass 5
   "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
   "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
-  "mips_store_data_bypass_p")
+  "!mips_store_data_bypass_p")
 
 ;; mf{hi,lo} is 1 cycle.  
 
@@ -351,7 +351,7 @@
 (define_bypass 7
   "ir_sb1_mulsi,ir_sb1_muldi"
   "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
-  "mips_store_data_bypass_p")
+  "!mips_store_data_bypass_p")
 
 ;; The divide unit is not pipelined.  Divide busy is asserted in the 4th
 ;; cycle, and then deasserted on the latency cycle.  So only one divide at