diff options
| author | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-12-10 00:41:17 +0000 |
|---|---|---|
| committer | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-12-10 00:41:17 +0000 |
| commit | 278e7895c8d7049fdfbd2b8174baf54a4c720ee6 (patch) | |
| tree | 418ecfd5d7c4941fbc9fb107b954fee46f02ef7b /gcc/config/pa/pa.c | |
| parent | 9820cc9f1cf01c81d5abf9b02a7fe70fcf6d3a3f (diff) | |
| download | gcc-278e7895c8d7049fdfbd2b8174baf54a4c720ee6.tar.gz | |
PR target/68729
* config/pa/pa.c (pa_emit_move_sequence): Don't check that mode is
consistent with modes of the input and output operands when doing
reloads to and from floating point registers. Do reload for all
address forms.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231482 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/pa/pa.c')
| -rw-r--r-- | gcc/config/pa/pa.c | 22 |
1 files changed, 8 insertions, 14 deletions
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index b8caab52319..50424c769b7 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -1683,11 +1683,10 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) REG+D addresses where D does not fit in 5 or 14 bits, including (subreg (mem (addr))) cases. */ if (scratch_reg - && fp_reg_operand (operand0, mode) + && FP_REG_P (operand0) && (MEM_P (operand1) || (GET_CODE (operand1) == SUBREG - && MEM_P (XEXP (operand1, 0)))) - && !floating_point_store_memory_operand (operand1, mode)) + && MEM_P (XEXP (operand1, 0))))) { if (GET_CODE (operand1) == SUBREG) operand1 = XEXP (operand1, 0); @@ -1699,10 +1698,8 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) /* D might not fit in 14 bits either; for such cases load D into scratch reg. */ - if (reg_plus_base_memory_operand (operand1, mode) - && !(TARGET_PA_20 - && !TARGET_ELF32 - && INT_14_BITS (XEXP (XEXP (operand1, 0), 1)))) + if (reg_plus_base_memory_operand (operand1, GET_MODE (operand1)) + && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))) { emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); emit_move_insn (scratch_reg, @@ -1718,11 +1715,10 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) return 1; } else if (scratch_reg - && fp_reg_operand (operand1, mode) + && FP_REG_P (operand1) && (MEM_P (operand0) || (GET_CODE (operand0) == SUBREG - && MEM_P (XEXP (operand0, 0)))) - && !floating_point_store_memory_operand (operand0, mode)) + && MEM_P (XEXP (operand0, 0))))) { if (GET_CODE (operand0) == SUBREG) operand0 = XEXP (operand0, 0); @@ -1734,10 +1730,8 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) /* D might not fit in 14 bits either; for such cases load D into scratch reg. */ - if (reg_plus_base_memory_operand (operand0, mode) - && !(TARGET_PA_20 - && !TARGET_ELF32 - && INT_14_BITS (XEXP (XEXP (operand0, 0), 1)))) + if (reg_plus_base_memory_operand (operand0, GET_MODE (operand0)) + && !INT_14_BITS (XEXP (XEXP (operand0, 0), 1))) { emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, |