diff options
author | kazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-02-20 02:26:06 +0000 |
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committer | kazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-02-20 02:26:06 +0000 |
commit | 5b865fafa95bf4d26de8ead98df5c0a2a1572e3b (patch) | |
tree | c743bf814d7cb42b897746f31213730d00e36ae4 /gcc/config/pa | |
parent | 85c36fd1d38e057cd4147384cc4b876238db988a (diff) | |
download | gcc-5b865fafa95bf4d26de8ead98df5c0a2a1572e3b.tar.gz |
* config/c4x/c4x.md, config/cris/cris.c, config/crx/crx.c,
config/fr30/fr30.md, config/i386/i386.h,
config/iq2000/iq2000.h, config/iq2000/predicates.md,
config/pa/milli64.S, config/pa/pa.c, config/pa/pa.h,
config/pa/pa.md, config/pa/pa32-regs.h, config/pa/pa64-regs.h,
config/pdp11/pdp11.c, config/pdp11/pdp11.h,
config/rs6000/altivec.md, config/rs6000/rs6000.c,
config/s390/s390-modes.def, config/sparc/netbsd-elf.h,
config/sparc/sparc.c, config/sparc/sparc.h,
config/sparc/sparc.md, config/spu/constraints.md,
config/spu/spu.c, config/stormy16/stormy16.md: Follow spelling
conventions.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@122151 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/pa')
-rw-r--r-- | gcc/config/pa/milli64.S | 4 | ||||
-rw-r--r-- | gcc/config/pa/pa.c | 2 | ||||
-rw-r--r-- | gcc/config/pa/pa.h | 8 | ||||
-rw-r--r-- | gcc/config/pa/pa.md | 2 | ||||
-rw-r--r-- | gcc/config/pa/pa32-regs.h | 2 | ||||
-rw-r--r-- | gcc/config/pa/pa64-regs.h | 2 |
6 files changed, 10 insertions, 10 deletions
diff --git a/gcc/config/pa/milli64.S b/gcc/config/pa/milli64.S index eb8fed105e0..ffcafa30a6d 100644 --- a/gcc/config/pa/milli64.S +++ b/gcc/config/pa/milli64.S @@ -411,7 +411,7 @@ LSYM(small_divisor) #if defined(pa64) /* Clear the upper 32 bits of the arg1 register. We are working with */ -/* small divisors (and 32 bit integers) We must not be mislead */ +/* small divisors (and 32-bit integers) We must not be mislead */ /* by "1" bits left in the upper 32 bits. */ depd %r0,31,32,%r25 #endif @@ -626,7 +626,7 @@ LSYM(special_divisor) #if defined(pa64) /* Clear the upper 32 bits of the arg1 register. We are working with - small divisors (and 32 bit unsigned integers) We must not be mislead + small divisors (and 32-bit unsigned integers) We must not be mislead by "1" bits left in the upper 32 bits. */ depd %r0,31,32,%r25 #endif diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index b63239808f7..e39ddc79a32 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -576,7 +576,7 @@ adddi3_operand (rtx op, enum machine_mode mode) } /* True iff zdepi can be used to generate this CONST_INT. - zdepi first sign extends a 5 bit signed number to a given field + zdepi first sign extends a 5-bit signed number to a given field length, then places this field anywhere in a zero. */ int zdepi_cint_p (unsigned HOST_WIDE_INT x) diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 853de9871fd..60a72459581 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -487,10 +487,10 @@ extern struct rtx_def *hppa_pic_save_rtx (void); C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. - `I' is used for the 11 bit constants. - `J' is used for the 14 bit constants. + `I' is used for the 11-bit constants. + `J' is used for the 14-bit constants. `K' is used for values that can be moved with a zdepi insn. - `L' is used for the 5 bit constants. + `L' is used for the 5-bit constants. `M' is used for 0. `N' is used for values with the least significant 11 bits equal to zero and when sign extended from 32 to 64 bits the @@ -1321,7 +1321,7 @@ extern int may_call_alloca; function's constant-pool, because such addresses can actually be output as REG+SMALLINT. - Note we only allow 5 bit immediates for access to a constant address; + Note we only allow 5-bit immediates for access to a constant address; doing so avoids losing for loading/storing a FP register at an address which will not fit in 5 bits. */ diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 61dbb46992e..d686cb82b57 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -4638,7 +4638,7 @@ "!TARGET_64BIT" "* { - /* Don't output a 64 bit constant, since we can't trust the assembler to + /* Don't output a 64-bit constant, since we can't trust the assembler to handle it correctly. */ if (GET_CODE (operands[2]) == CONST_DOUBLE) operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2])); diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h index a17c117726a..fa0f0f9c36e 100644 --- a/gcc/config/pa/pa32-regs.h +++ b/gcc/config/pa/pa32-regs.h @@ -15,7 +15,7 @@ HP-PA 1.1 has 32 fullword registers and 32 floating point registers. However, the floating point registers behave differently: the left and right halves of registers are addressable - as 32 bit registers. So, we will set things up like the 68k which + as 32-bit registers. So, we will set things up like the 68k which has different fp units: define separate register sets for the 1.0 and 1.1 fp units. */ diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h index cbf2d981c6c..e356407f8fd 100644 --- a/gcc/config/pa/pa64-regs.h +++ b/gcc/config/pa/pa64-regs.h @@ -31,7 +31,7 @@ Boston, MA 02110-1301, USA. */ HP-PA 2.0w has 32 fullword registers and 32 floating point registers. However, the floating point registers behave differently: the left and right halves of registers are addressable - as 32 bit registers. + as 32-bit registers. Due to limitations within GCC itself, we do not expose the left/right half addressability when in wide mode. This is not a major performance |