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| author | segher <segher@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-05-23 16:41:20 +0000 |
|---|---|---|
| committer | segher <segher@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-05-23 16:41:20 +0000 |
| commit | 7d307a6aea683889259b036216e134ef23738ccb (patch) | |
| tree | 9b3fa581539d8e25c226995953241901f465231f /gcc/config/rs6000/cell.md | |
| parent | 90e4483f4e6b64239bdff4c1c83d8550f367153e (diff) | |
| download | gcc-7d307a6aea683889259b036216e134ef23738ccb.tar.gz | |
rs6000: Make all shift instructions one type
This uses the attributes "var_shift" and "dot" to specify the differences:
var_shift_rotate -> shift var_shift=yes
delayed_compare -> shift var_shift=no dot=yes
var_delayed_compare -> shift var_shift=yes dot=yes
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210870 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/cell.md')
| -rw-r--r-- | gcc/config/rs6000/cell.md | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md index 1bf308eec3d..923524d7233 100644 --- a/gcc/config/rs6000/cell.md +++ b/gcc/config/rs6000/cell.md @@ -166,8 +166,9 @@ ;; Integer latency is 2 cycles (define_insn_reservation "cell-integer" 2 - (and (ior (eq_attr "type" "integer,shift,trap,\ - var_shift_rotate,cntlz,exts,isel") + (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel") + (and (eq_attr "type" "shift") + (eq_attr "dot" "no")) (and (eq_attr "type" "insert") (eq_attr "size" "64"))) (eq_attr "cpu" "cell")) @@ -200,17 +201,19 @@ ;; add, addo, sub, subo, alter cr0, rldcli, rlwinm (define_insn_reservation "cell-fast-cmp" 2 - (and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\ - var_delayed_compare") - (eq_attr "cpu" "cell")) - (eq_attr "cell_micro" "not")) + (and (ior (eq_attr "type" "fast_compare,compare") + (and (eq_attr "type" "shift") + (eq_attr "dot" "yes"))) + (eq_attr "cpu" "cell") + (eq_attr "cell_micro" "not")) "slot01,fxu_cell") (define_insn_reservation "cell-cmp-microcoded" 9 - (and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\ - var_delayed_compare") - (eq_attr "cpu" "cell")) - (eq_attr "cell_micro" "always")) + (and (ior (eq_attr "type" "fast_compare,compare") + (and (eq_attr "type" "shift") + (eq_attr "dot" "yes"))) + (eq_attr "cpu" "cell") + (eq_attr "cell_micro" "always")) "slot0+slot1,fxu_cell,fxu_cell*7") ;; mulld |