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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2015-11-25 22:49:41 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2015-11-25 22:49:41 +0000 |
| commit | d5906efcaa2b75bc7991909cf56f934d141ecbdb (patch) | |
| tree | 7526c55451b8bf3ed828f529ef373b6378be87b8 /gcc/config/rs6000/constraints.md | |
| parent | 22bea0be95010c6efc39649d06e0f15c90ca38c4 (diff) | |
| download | gcc-d5906efcaa2b75bc7991909cf56f934d141ecbdb.tar.gz | |
<patch #10>
[gcc]
2015-11-25 Michael Meissner <meissner@linux.vnet.ibm.com>
<patch #10>
* config/rs6000/constraints.md (wb constraint): New constraint for
ISA 3.0 d-form scalar addressing.
* config/rs6000/rs6000.c (mode_supports_vmx_dform): Add support
for ISA 3.0 D-form addressing to load SFmode/DFmode scalars into
Altivec registers. Add wb constraint for Altivec registers with
D-form addressing. If we have ISA 3.0 d-form support, undo
secondary reload support for using FPR registers if we want to do
D-form addressing.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_secondary_reload): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wb
constraint.
* config/rs6000/rs6000.md (f32_lr2 mode attribute): Add support
for ISA 3.0 SFmode/DFmode d-form addressing to Altivec registers.
(f32_lm2): Likewise.
(f32_li2): Likewise.
(f32_sr2): Likewise.
(f32_sm2): Likewise.
(f32_si2): Likewise.
(f64_p9): Likewise.
(extendsfdf2_fpr): Likewise.
(mov<mode>_hardfloat): Likewise.
(mov<mode>_hardfloat32): Likewise.
(mov<mode>_hardfloat64): Likewise.
* doc/md.texi (RS/6000 constraints): Document wb constraint.
Fixup we constraint documentation.
[gcc/testsuite]
2015-11-25 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/dform-1.c: New test.
* gcc.target/powerpc/dform-2.c: Likewise.
From-SVN: r230913
Diffstat (limited to 'gcc/config/rs6000/constraints.md')
| -rw-r--r-- | gcc/config/rs6000/constraints.md | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index e4129453736..1e7f27b7d6f 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -56,7 +56,8 @@ (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" "Any VSX register if the -mvsx option was used or NO_REGS.") -;; wb is not currently used +(define_register_constraint "wb" "rs6000_constraints[RS6000_CONSTRAINT_wb]" + "Altivec register if the -mpower9-dform option was used or NO_REGS.") ;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits. ;; It is currently used for that purpose in LLVM. |