[gcc]

2014-03-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/vector.md (VEC_L): Add V1TI mode to vector types.
	(VEC_M): Likewise.
	(VEC_N): Likewise.
	(VEC_R): Likewise.
	(VEC_base): Likewise.
	(mov<MODE>, VEC_M modes): If we are loading TImode into VSX
	registers, we need to swap double words in little endian mode.

	* config/rs6000/rs6000-modes.def (V1TImode): Add new vector mode
	to be a container mode for 128-bit integer operations added in ISA
	2.07.  Unlike TImode and PTImode, the preferred register set is
	the Altivec/VMX registers for the 128-bit operations.

	* config/rs6000/rs6000-protos.h (rs6000_move_128bit_ok_p): Add
	declarations.
	(rs6000_split_128bit_ok_p): Likewise.

	* config/rs6000/rs6000-builtin.def (BU_P8V_AV_3): Add new support
	macros for creating ISA 2.07 normal and overloaded builtin
	functions with 3 arguments.
	(BU_P8V_OVERLOAD_3): Likewise.
	(VPERM_1T): Add support for V1TImode in 128-bit vector operations
	for use as overloaded functions.
	(VPERM_1TI_UNS): Likewise.
	(VSEL_1TI): Likewise.
	(VSEL_1TI_UNS): Likewise.
	(ST_INTERNAL_1ti): Likewise.
	(LD_INTERNAL_1ti): Likewise.
	(XXSEL_1TI): Likewise.
	(XXSEL_1TI_UNS): Likewise.
	(VPERM_1TI): Likewise.
	(VPERM_1TI_UNS): Likewise.
	(XXPERMDI_1TI): Likewise.
	(SET_1TI): Likewise.
	(LXVD2X_V1TI): Likewise.
	(STXVD2X_V1TI): Likewise.
	(VEC_INIT_V1TI): Likewise.
	(VEC_SET_V1TI): Likewise.
	(VEC_EXT_V1TI): Likewise.
	(EQV_V1TI): Likewise.
	(NAND_V1TI): Likewise.
	(ORC_V1TI): Likewise.
	(VADDCUQ): Add support for 128-bit integer arithmetic instructions
	added in ISA 2.07.  Add both normal 'altivec' builtins, and the
	overloaded builtin.
	(VADDUQM): Likewise.
	(VSUBCUQ): Likewise.
	(VADDEUQM): Likewise.
	(VADDECUQ): Likewise.
	(VSUBEUQM): Likewise.
	(VSUBECUQ): Likewise.

	* config/rs6000/rs6000-c.c (__int128_type): New static to hold
	__int128_t and __uint128_t types.
	(__uint128_type): Likewise.
	(altivec_categorize_keyword): Add support for vector __int128_t,
	vector __uint128_t, vector __int128, and vector unsigned __int128
	as a container type for TImode operations that need to be done in
	VSX/Altivec registers.
	(rs6000_macro_to_expand): Likewise.
	(altivec_overloaded_builtins): Add ISA 2.07 overloaded functions
	to support 128-bit integer instructions vaddcuq, vadduqm,
	vaddecuq, vaddeuqm, vsubcuq, vsubuqm, vsubecuq, vsubeuqm.
	(altivec_resolve_overloaded_builtin): Add support for V1TImode.

	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Add support
	for V1TImode, and set up preferences to use VSX/Altivec
	registers.  Setup VSX reload handlers.
	(rs6000_debug_reg_global): Likewise.
	(rs6000_init_hard_regno_mode_ok): Likewise.
	(rs6000_preferred_simd_mode): Likewise.
	(vspltis_constant): Do not allow V1TImode as easy altivec
	constants.
	(easy_altivec_constant): Likewise.
	(output_vec_const_move): Likewise.
	(rs6000_expand_vector_set): Convert V1TImode set and extract to
	simple move.
	(rs6000_expand_vector_extract): Likewise.
	(reg_offset_addressing_ok_p): Setup V1TImode to use VSX reg+reg
	addressing.
	(rs6000_const_vec): Add support for V1TImode.
	(rs6000_emit_le_vsx_load): Swap double words when loading or
	storing TImode/V1TImode.
	(rs6000_emit_le_vsx_store): Likewise.
	(rs6000_emit_le_vsx_move): Likewise.
	(rs6000_emit_move): Add support for V1TImode.
	(altivec_expand_ld_builtin): Likewise.
	(altivec_expand_st_builtin): Likewise.
	(altivec_expand_vec_init_builtin): Likewise.
	(altivec_expand_builtin): Likewise.
	(rs6000_init_builtins): Add support for V1TImode type.  Add
	support for ISA 2.07 128-bit integer builtins.  Define type names
	for the VSX/Altivec vector types.
	(altivec_init_builtins): Add support for overloaded vector
	functions with V1TImode type.
	(rs6000_preferred_reload_class): Prefer Altivec registers for
	V1TImode.
	(rs6000_move_128bit_ok_p): Move 128-bit move/split validation to
	external function.
	(rs6000_split_128bit_ok_p): Likewise.
	(rs6000_handle_altivec_attribute): Create V1TImode from vector
	__int128_t and vector __uint128_t.

	* config/rs6000/vsx.md (VSX_L): Add V1TImode to vector iterators
	and mode attributes.
	(VSX_M): Likewise.
	(VSX_M2): Likewise.
	(VSm): Likewise.
	(VSs): Likewise.
	(VSr): Likewise.
	(VSv): Likewise.
	(VS_scalar): Likewise.
	(VS_double): Likewise.
	(vsx_set_v1ti): New builtin function to create V1TImode from
	TImode.

	* config/rs6000/rs6000.h (TARGET_VADDUQM): New macro to say
	whether we support the ISA 2.07 128-bit integer arithmetic
	instructions.
	(ALTIVEC_OR_VSX_VECTOR_MODE): Add V1TImode.
	(enum rs6000_builtin_type_index): Add fields to hold V1TImode
	and TImode types for use with the builtin functions.
	(V1TI_type_node): Likewise.
	(unsigned_V1TI_type_node): Likewise.
	(intTI_type_internal_node): Likewise.
	(uintTI_type_internal_node): Likewise.

	* config/rs6000/altivec.md (UNSPEC_VADDCUQ): New unspecs for ISA
	2.07 128-bit builtin functions.
	(UNSPEC_VADDEUQM): Likewise.
	(UNSPEC_VADDECUQ): Likewise.
	(UNSPEC_VSUBCUQ): Likewise.
	(UNSPEC_VSUBEUQM): Likewise.
	(UNSPEC_VSUBECUQ): Likewise.
	(VM): Add V1TImode to vector mode iterators.
	(VM2): Likewise.
	(VI_unit): Likewise.
	(altivec_vadduqm): Add ISA 2.07 128-bit binary builtins.
	(altivec_vaddcuq): Likewise.
	(altivec_vsubuqm): Likewise.
	(altivec_vsubcuq): Likewise.
	(altivec_vaddeuqm): Likewise.
	(altivec_vaddecuq): Likewise.
	(altivec_vsubeuqm): Likewise.
	(altivec_vsubecuq): Likewise.

	* config/rs6000/rs6000.md (FMOVE128_GPR): Add V1TImode to vector
	mode iterators.
	(BOOL_128): Likewise.
	(BOOL_REGS_OUTPUT): Likewise.
	(BOOL_REGS_OP1): Likewise.
	(BOOL_REGS_OP2): Likewise.
	(BOOL_REGS_UNARY): Likewise.
	(BOOL_REGS_AND_CR0): Likewise.

	* config/rs6000/altivec.h (vec_vaddcuq): Add support for ISA 2.07
	128-bit integer builtin support.
	(vec_vadduqm): Likewise.
	(vec_vaddecuq): Likewise.
	(vec_vaddeuqm): Likewise.
	(vec_vsubecuq): Likewise.
	(vec_vsubeuqm): Likewise.
	(vec_vsubcuq): Likewise.
	(vec_vsubuqm): Likewise.

	* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
	Document vec_vaddcuq, vec_vadduqm, vec_vaddecuq, vec_vaddeuqm,
	vec_subecuq, vec_subeuqm, vec_vsubcuq, vec_vsubeqm builtins adding
	128-bit integer add/subtract to ISA 2.07.

[gcc/testsuite]
2014-03-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p8vector-int128-1.c: New test to test ISA
	2.07 128-bit arithmetic.
	* gcc.target/powerpc/p8vector-int128-2.c: Likewise.

	* gcc.target/powerpc/timode_off.c: Restrict cpu type to power5,
	due to when TImode is allowed in VSX registers, the allowable
	address modes for TImode is just a single indirect address in
	order for the value to be loaded and store in either GPR or VSX
	registers.  This affects the generated code, and it would cause
	this test to fail, when such an option is used.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208522 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 56 insertions, 0 deletions

diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 46df66b7b73..9226035a3fd 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -325,6 +325,14 @@
 		     | RS6000_BTC_BINARY),				\
 		    CODE_FOR_ ## ICODE)			/* ICODE */
 
+#define BU_P8V_AV_3(ENUM, NAME, ATTR, ICODE)				\
+  RS6000_BUILTIN_3 (P8V_BUILTIN_ ## ENUM,		/* ENUM */	\
+		    "__builtin_altivec_" NAME,		/* NAME */	\
+		    RS6000_BTM_P8_VECTOR,		/* MASK */	\
+		    (RS6000_BTC_ ## ATTR		/* ATTR */	\
+		     | RS6000_BTC_TERNARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
+
 #define BU_P8V_AV_P(ENUM, NAME, ATTR, ICODE)				\
   RS6000_BUILTIN_P (P8V_BUILTIN_ ## ENUM,		/* ENUM */	\
 		    "__builtin_altivec_" NAME,		/* NAME */	\
@@ -359,6 +367,14 @@
 		     | RS6000_BTC_BINARY),				\
 		    CODE_FOR_nothing)			/* ICODE */
 
+#define BU_P8V_OVERLOAD_3(ENUM, NAME)					\
+  RS6000_BUILTIN_3 (P8V_BUILTIN_VEC_ ## ENUM,		/* ENUM */	\
+		    "__builtin_vec_" NAME,		/* NAME */	\
+		    RS6000_BTM_P8_VECTOR,		/* MASK */	\
+		    (RS6000_BTC_OVERLOADED		/* ATTR */	\
+		     | RS6000_BTC_TERNARY),				\
+		    CODE_FOR_nothing)			/* ICODE */
+
 /* Crypto convenience macros.  */
 #define BU_CRYPTO_1(ENUM, NAME, ATTR, ICODE)				\
   RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM,		/* ENUM */	\
@@ -571,12 +587,14 @@ BU_ALTIVEC_3 (VMSUMSHM,       "vmsumshm",       CONST, 	altivec_vmsumshm)
 BU_ALTIVEC_3 (VMSUMUHS,       "vmsumuhs",       SAT,   	altivec_vmsumuhs)
 BU_ALTIVEC_3 (VMSUMSHS,       "vmsumshs",       SAT,   	altivec_vmsumshs)
 BU_ALTIVEC_3 (VNMSUBFP,       "vnmsubfp",       FP,    	nfmsv4sf4)
+BU_ALTIVEC_3 (VPERM_1TI,      "vperm_1ti",      CONST, 	altivec_vperm_v1ti)
 BU_ALTIVEC_3 (VPERM_2DF,      "vperm_2df",      CONST, 	altivec_vperm_v2df)
 BU_ALTIVEC_3 (VPERM_2DI,      "vperm_2di",      CONST, 	altivec_vperm_v2di)
 BU_ALTIVEC_3 (VPERM_4SF,      "vperm_4sf",      CONST, 	altivec_vperm_v4sf)
 BU_ALTIVEC_3 (VPERM_4SI,      "vperm_4si",      CONST, 	altivec_vperm_v4si)
 BU_ALTIVEC_3 (VPERM_8HI,      "vperm_8hi",      CONST, 	altivec_vperm_v8hi)
 BU_ALTIVEC_3 (VPERM_16QI,     "vperm_16qi",     CONST, 	altivec_vperm_v16qi_uns)
+BU_ALTIVEC_3 (VPERM_1TI_UNS,  "vperm_1ti_uns",  CONST, 	altivec_vperm_v1ti_uns)
 BU_ALTIVEC_3 (VPERM_2DI_UNS,  "vperm_2di_uns",  CONST, 	altivec_vperm_v2di_uns)
 BU_ALTIVEC_3 (VPERM_4SI_UNS,  "vperm_4si_uns",  CONST, 	altivec_vperm_v4si_uns)
 BU_ALTIVEC_3 (VPERM_8HI_UNS,  "vperm_8hi_uns",  CONST, 	altivec_vperm_v8hi_uns)
@@ -587,10 +605,12 @@ BU_ALTIVEC_3 (VSEL_8HI,       "vsel_8hi",       CONST, 	vector_select_v8hi)
 BU_ALTIVEC_3 (VSEL_16QI,      "vsel_16qi",      CONST, 	vector_select_v16qi)
 BU_ALTIVEC_3 (VSEL_2DF,       "vsel_2df",       CONST, 	vector_select_v2df)
 BU_ALTIVEC_3 (VSEL_2DI,       "vsel_2di",       CONST, 	vector_select_v2di)
+BU_ALTIVEC_3 (VSEL_1TI,       "vsel_1ti",       CONST, 	vector_select_v1ti)
 BU_ALTIVEC_3 (VSEL_4SI_UNS,   "vsel_4si_uns",   CONST, 	vector_select_v4si_uns)
 BU_ALTIVEC_3 (VSEL_8HI_UNS,   "vsel_8hi_uns",   CONST, 	vector_select_v8hi_uns)
 BU_ALTIVEC_3 (VSEL_16QI_UNS,  "vsel_16qi_uns",  CONST, 	vector_select_v16qi_uns)
 BU_ALTIVEC_3 (VSEL_2DI_UNS,   "vsel_2di_uns",   CONST, 	vector_select_v2di_uns)
+BU_ALTIVEC_3 (VSEL_1TI_UNS,   "vsel_1ti_uns",   CONST, 	vector_select_v1ti_uns)
 BU_ALTIVEC_3 (VSLDOI_16QI,    "vsldoi_16qi",    CONST, 	altivec_vsldoi_v16qi)
 BU_ALTIVEC_3 (VSLDOI_8HI,     "vsldoi_8hi",     CONST, 	altivec_vsldoi_v8hi)
 BU_ALTIVEC_3 (VSLDOI_4SI,     "vsldoi_4si",     CONST, 	altivec_vsldoi_v4si)
@@ -783,6 +803,8 @@ BU_ALTIVEC_X (ST_INTERNAL_2df,	"st_internal_4sf",  MEM)
 BU_ALTIVEC_X (LD_INTERNAL_2df,	"ld_internal_2df",  MEM)
 BU_ALTIVEC_X (ST_INTERNAL_2di,	"st_internal_2di",  MEM)
 BU_ALTIVEC_X (LD_INTERNAL_2di,	"ld_internal_2di",  MEM)
+BU_ALTIVEC_X (ST_INTERNAL_1ti,	"st_internal_1ti",  MEM)
+BU_ALTIVEC_X (LD_INTERNAL_1ti,	"ld_internal_1ti",  MEM)
 BU_ALTIVEC_X (MTVSCR,		"mtvscr",	    MISC)
 BU_ALTIVEC_X (MFVSCR,		"mfvscr",	    MISC)
 BU_ALTIVEC_X (DSSALL,		"dssall",	    MISC)
@@ -1085,34 +1107,40 @@ BU_VSX_3 (XVMSUBDP,           "xvmsubdp",       CONST, 	fmsv2df4)
 BU_VSX_3 (XVNMADDDP,          "xvnmadddp",      CONST, 	nfmav2df4)
 BU_VSX_3 (XVNMSUBDP,          "xvnmsubdp",      CONST, 	nfmsv2df4)
 
+BU_VSX_3 (XXSEL_1TI,          "xxsel_1ti",      CONST, 	vector_select_v1ti)
 BU_VSX_3 (XXSEL_2DI,          "xxsel_2di",      CONST, 	vector_select_v2di)
 BU_VSX_3 (XXSEL_2DF,          "xxsel_2df",      CONST, 	vector_select_v2df)
 BU_VSX_3 (XXSEL_4SF,          "xxsel_4sf",      CONST, 	vector_select_v4sf)
 BU_VSX_3 (XXSEL_4SI,          "xxsel_4si",      CONST, 	vector_select_v4si)
 BU_VSX_3 (XXSEL_8HI,          "xxsel_8hi",      CONST, 	vector_select_v8hi)
 BU_VSX_3 (XXSEL_16QI,         "xxsel_16qi",     CONST, 	vector_select_v16qi)
+BU_VSX_3 (XXSEL_1TI_UNS,      "xxsel_1ti_uns",  CONST, 	vector_select_v1ti_uns)
 BU_VSX_3 (XXSEL_2DI_UNS,      "xxsel_2di_uns",  CONST, 	vector_select_v2di_uns)
 BU_VSX_3 (XXSEL_4SI_UNS,      "xxsel_4si_uns",  CONST, 	vector_select_v4si_uns)
 BU_VSX_3 (XXSEL_8HI_UNS,      "xxsel_8hi_uns",  CONST, 	vector_select_v8hi_uns)
 BU_VSX_3 (XXSEL_16QI_UNS,     "xxsel_16qi_uns", CONST, 	vector_select_v16qi_uns)
 
+BU_VSX_3 (VPERM_1TI,          "vperm_1ti",      CONST, 	altivec_vperm_v1ti)
 BU_VSX_3 (VPERM_2DI,          "vperm_2di",      CONST, 	altivec_vperm_v2di)
 BU_VSX_3 (VPERM_2DF,          "vperm_2df",      CONST, 	altivec_vperm_v2df)
 BU_VSX_3 (VPERM_4SF,          "vperm_4sf",      CONST, 	altivec_vperm_v4sf)
 BU_VSX_3 (VPERM_4SI,          "vperm_4si",      CONST, 	altivec_vperm_v4si)
 BU_VSX_3 (VPERM_8HI,          "vperm_8hi",      CONST, 	altivec_vperm_v8hi)
 BU_VSX_3 (VPERM_16QI,         "vperm_16qi",     CONST, 	altivec_vperm_v16qi)
+BU_VSX_3 (VPERM_1TI_UNS,      "vperm_1ti_uns",  CONST, 	altivec_vperm_v1ti_uns)
 BU_VSX_3 (VPERM_2DI_UNS,      "vperm_2di_uns",  CONST, 	altivec_vperm_v2di_uns)
 BU_VSX_3 (VPERM_4SI_UNS,      "vperm_4si_uns",  CONST, 	altivec_vperm_v4si_uns)
 BU_VSX_3 (VPERM_8HI_UNS,      "vperm_8hi_uns",  CONST, 	altivec_vperm_v8hi_uns)
 BU_VSX_3 (VPERM_16QI_UNS,     "vperm_16qi_uns", CONST, 	altivec_vperm_v16qi_uns)
 
+BU_VSX_3 (XXPERMDI_1TI,       "xxpermdi_1ti",   CONST, 	vsx_xxpermdi_v1ti)
 BU_VSX_3 (XXPERMDI_2DF,       "xxpermdi_2df",   CONST, 	vsx_xxpermdi_v2df)
 BU_VSX_3 (XXPERMDI_2DI,       "xxpermdi_2di",   CONST, 	vsx_xxpermdi_v2di)
 BU_VSX_3 (XXPERMDI_4SF,       "xxpermdi_4sf",   CONST, 	vsx_xxpermdi_v4sf)
 BU_VSX_3 (XXPERMDI_4SI,       "xxpermdi_4si",   CONST, 	vsx_xxpermdi_v4si)
 BU_VSX_3 (XXPERMDI_8HI,       "xxpermdi_8hi",   CONST, 	vsx_xxpermdi_v8hi)
 BU_VSX_3 (XXPERMDI_16QI,      "xxpermdi_16qi",  CONST, 	vsx_xxpermdi_v16qi)
+BU_VSX_3 (SET_1TI,            "set_1ti",        CONST, 	vsx_set_v1ti)
 BU_VSX_3 (SET_2DF,            "set_2df",        CONST, 	vsx_set_v2df)
 BU_VSX_3 (SET_2DI,            "set_2di",        CONST, 	vsx_set_v2di)
 BU_VSX_3 (XXSLDWI_2DI,        "xxsldwi_2di",    CONST, 	vsx_xxsldwi_v2di)
@@ -1247,6 +1275,7 @@ BU_VSX_P (XVCMPGTDP_P,	      "xvcmpgtdp_p",	CONST,	vector_gt_v2df_p)
 
 /* VSX builtins that are handled as special cases.  */
 BU_VSX_X (LXSDX,	      "lxsdx",		MEM)
+BU_VSX_X (LXVD2X_V1TI,	      "lxvd2x_v1ti",	MEM)
 BU_VSX_X (LXVD2X_V2DF,	      "lxvd2x_v2df",	MEM)
 BU_VSX_X (LXVD2X_V2DI,	      "lxvd2x_v2di",	MEM)
 BU_VSX_X (LXVDSX,	      "lxvdsx",		MEM)
@@ -1255,6 +1284,7 @@ BU_VSX_X (LXVW4X_V4SI,        "lxvw4x_v4si",	MEM)
 BU_VSX_X (LXVW4X_V8HI,        "lxvw4x_v8hi",	MEM)
 BU_VSX_X (LXVW4X_V16QI,	      "lxvw4x_v16qi",	MEM)
 BU_VSX_X (STXSDX,	      "stxsdx",		MEM)
+BU_VSX_X (STXVD2X_V1TI,	      "stxsdx_v1ti",	MEM)
 BU_VSX_X (STXVD2X_V2DF,	      "stxsdx_v2df",	MEM)
 BU_VSX_X (STXVD2X_V2DI,	      "stxsdx_v2di",	MEM)
 BU_VSX_X (STXVW4X_V4SF,	      "stxsdx_v4sf",	MEM)
@@ -1285,10 +1315,13 @@ BU_VSX_X (XSNMADDMDP,	      "xsnmaddmdp",	FP)
 BU_VSX_X (XSNMSUBADP,	      "xsnmsubadp",	FP)
 BU_VSX_X (XSNMSUBMDP,	      "xsnmsubmdp",	FP)
 BU_VSX_X (XSSUBDP,	      "xssubdp",	FP)
+BU_VSX_X (VEC_INIT_V1TI,      "vec_init_v1ti",	CONST)
 BU_VSX_X (VEC_INIT_V2DF,      "vec_init_v2df",	CONST)
 BU_VSX_X (VEC_INIT_V2DI,      "vec_init_v2di",	CONST)
+BU_VSX_X (VEC_SET_V1TI,	      "vec_set_v1ti",	CONST)
 BU_VSX_X (VEC_SET_V2DF,	      "vec_set_v2df",	CONST)
 BU_VSX_X (VEC_SET_V2DI,	      "vec_set_v2di",	CONST)
+BU_VSX_X (VEC_EXT_V1TI,	      "vec_ext_v1ti",	CONST)
 BU_VSX_X (VEC_EXT_V2DF,	      "vec_ext_v2df",	CONST)
 BU_VSX_X (VEC_EXT_V2DI,	      "vec_ext_v2di",	CONST)
 
@@ -1332,7 +1365,9 @@ BU_P8V_AV_1 (VPOPCNTD,	      "vpopcntd",	CONST,  popcountv2di2)
 BU_P8V_AV_1 (VGBBD,	      "vgbbd",		CONST,  p8v_vgbbd)
 
 /* 2 argument altivec instructions added in ISA 2.07.  */
+BU_P8V_AV_2 (VADDCUQ,		"vaddcuq",	CONST,	altivec_vaddcuq)
 BU_P8V_AV_2 (VADDUDM,		"vaddudm",	CONST,	addv2di3)
+BU_P8V_AV_2 (VADDUQM,		"vadduqm",	CONST,	altivec_vadduqm)
 BU_P8V_AV_2 (VMINSD,		"vminsd",	CONST,	sminv2di3)
 BU_P8V_AV_2 (VMAXSD,		"vmaxsd",	CONST,	smaxv2di3)
 BU_P8V_AV_2 (VMINUD,		"vminud",	CONST,	uminv2di3)
@@ -1347,12 +1382,15 @@ BU_P8V_AV_2 (VRLD,		"vrld",		CONST,	vrotlv2di3)
 BU_P8V_AV_2 (VSLD,		"vsld",		CONST,	vashlv2di3)
 BU_P8V_AV_2 (VSRD,		"vsrd",		CONST,	vlshrv2di3)
 BU_P8V_AV_2 (VSRAD,		"vsrad",	CONST,	vashrv2di3)
+BU_P8V_AV_2 (VSUBCUQ,		"vsubcuq",	CONST,	altivec_vsubcuq)
 BU_P8V_AV_2 (VSUBUDM,		"vsubudm",	CONST,	subv2di3)
+BU_P8V_AV_2 (VSUBUQM,		"vsubuqm",	CONST,	altivec_vsubuqm)
 
 BU_P8V_AV_2 (EQV_V16QI,		"eqv_v16qi",	CONST,	eqvv16qi3)
 BU_P8V_AV_2 (EQV_V8HI,		"eqv_v8hi",	CONST,	eqvv8hi3)
 BU_P8V_AV_2 (EQV_V4SI,		"eqv_v4si",	CONST,	eqvv4si3)
 BU_P8V_AV_2 (EQV_V2DI,		"eqv_v2di",	CONST,	eqvv2di3)
+BU_P8V_AV_2 (EQV_V1TI,		"eqv_v1ti",	CONST,	eqvv1ti3)
 BU_P8V_AV_2 (EQV_V4SF,		"eqv_v4sf",	CONST,	eqvv4sf3)
 BU_P8V_AV_2 (EQV_V2DF,		"eqv_v2df",	CONST,	eqvv2df3)
 
@@ -1360,6 +1398,7 @@ BU_P8V_AV_2 (NAND_V16QI,	"nand_v16qi",	CONST,	nandv16qi3)
 BU_P8V_AV_2 (NAND_V8HI,		"nand_v8hi",	CONST,	nandv8hi3)
 BU_P8V_AV_2 (NAND_V4SI,		"nand_v4si",	CONST,	nandv4si3)
 BU_P8V_AV_2 (NAND_V2DI,		"nand_v2di",	CONST,	nandv2di3)
+BU_P8V_AV_2 (NAND_V1TI,		"nand_v1ti",	CONST,	nandv1ti3)
 BU_P8V_AV_2 (NAND_V4SF,		"nand_v4sf",	CONST,	nandv4sf3)
 BU_P8V_AV_2 (NAND_V2DF,		"nand_v2df",	CONST,	nandv2df3)
 
@@ -1367,9 +1406,16 @@ BU_P8V_AV_2 (ORC_V16QI,		"orc_v16qi",	CONST,	orcv16qi3)
 BU_P8V_AV_2 (ORC_V8HI,		"orc_v8hi",	CONST,	orcv8hi3)
 BU_P8V_AV_2 (ORC_V4SI,		"orc_v4si",	CONST,	orcv4si3)
 BU_P8V_AV_2 (ORC_V2DI,		"orc_v2di",	CONST,	orcv2di3)
+BU_P8V_AV_2 (ORC_V1TI,		"orc_v1ti",	CONST,	orcv1ti3)
 BU_P8V_AV_2 (ORC_V4SF,		"orc_v4sf",	CONST,	orcv4sf3)
 BU_P8V_AV_2 (ORC_V2DF,		"orc_v2df",	CONST,	orcv2df3)
 
+/* 3 argument altivec instructions added in ISA 2.07.  */
+BU_P8V_AV_3 (VADDEUQM,		"vaddeuqm",	 CONST,	altivec_vaddeuqm)
+BU_P8V_AV_3 (VADDECUQ,		"vaddecuq",	 CONST,	altivec_vaddecuq)
+BU_P8V_AV_3 (VSUBEUQM,		"vsubeuqm",	 CONST,	altivec_vsubeuqm)
+BU_P8V_AV_3 (VSUBECUQ,		"vsubecuq",	 CONST,	altivec_vsubecuq)
+
 /* Vector comparison instructions added in ISA 2.07.  */
 BU_P8V_AV_2 (VCMPEQUD,		"vcmpequd",	CONST,	vector_eqv2di)
 BU_P8V_AV_2 (VCMPGTSD,		"vcmpgtsd",	CONST,	vector_gtv2di)
@@ -1399,7 +1445,9 @@ BU_P8V_OVERLOAD_1 (VGBBD,	"vgbbd")
 BU_P8V_OVERLOAD_2 (EQV,		"eqv")
 BU_P8V_OVERLOAD_2 (NAND,	"nand")
 BU_P8V_OVERLOAD_2 (ORC,		"orc")
+BU_P8V_OVERLOAD_2 (VADDCUQ,	"vaddcuq")
 BU_P8V_OVERLOAD_2 (VADDUDM,	"vaddudm")
+BU_P8V_OVERLOAD_2 (VADDUQM,	"vadduqm")
 BU_P8V_OVERLOAD_2 (VMAXSD,	"vmaxsd")
 BU_P8V_OVERLOAD_2 (VMAXUD,	"vmaxud")
 BU_P8V_OVERLOAD_2 (VMINSD,	"vminsd")
@@ -1414,7 +1462,15 @@ BU_P8V_OVERLOAD_2 (VRLD,	"vrld")
 BU_P8V_OVERLOAD_2 (VSLD,	"vsld")
 BU_P8V_OVERLOAD_2 (VSRAD,	"vsrad")
 BU_P8V_OVERLOAD_2 (VSRD,	"vsrd")
+BU_P8V_OVERLOAD_2 (VSUBCUQ,	"vsubcuq")
 BU_P8V_OVERLOAD_2 (VSUBUDM,	"vsubudm")
+BU_P8V_OVERLOAD_2 (VSUBUQM,	"vsubuqm")
+
+/* ISA 2.07 vector overloaded 3 argument functions.  */
+BU_P8V_OVERLOAD_3 (VADDECUQ,	"vaddecuq")
+BU_P8V_OVERLOAD_3 (VADDEUQM,	"vaddeuqm")
+BU_P8V_OVERLOAD_3 (VSUBECUQ,	"vsubecuq")
+BU_P8V_OVERLOAD_3 (VSUBEUQM,	"vsubeuqm")
 
 
 /* 1 argument crypto functions.  */