diff options
| author | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-03-26 04:07:21 +0000 |
|---|---|---|
| committer | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-03-26 04:07:21 +0000 |
| commit | 3f26f29de1336cf48ae78922307b7e449ccf7f9c (patch) | |
| tree | f8bca2f0543f3731835379de20cc574bf158e79f /gcc/config/rs6000/rs6000.md | |
| parent | 6c87c4d94adab653b9a246f9386c5f2cc74efc05 (diff) | |
| download | gcc-3f26f29de1336cf48ae78922307b7e449ccf7f9c.tar.gz | |
2015-03-25 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/65569
* config/rs6000/rs6000.md (extenddftf2_fprs): On VSX systems use
XXLXOR to create 0.0. On pre-VSX systems make sure the constant
0.0 is correctly setup.
(extenddftf2_internal): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@221683 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index aec696e385a..da962877057 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8357,16 +8357,21 @@ && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" { - operands[2] = CONST0_RTX (DFmode); - /* Generate GOT reference early for SVR4 PIC. */ - if (DEFAULT_ABI == ABI_V4 && flag_pic) - operands[2] = validize_mem (force_const_mem (DFmode, operands[2])); + /* VSX can create 0.0 directly, otherwise let rs6000_emit_move create + the proper constant. */ + if (TARGET_VSX) + operands[2] = CONST0_RTX (DFmode); + else + { + operands[2] = gen_reg_rtx (DFmode); + rs6000_emit_move (operands[2], CONST0_RTX (DFmode), DFmode); + } }) (define_insn_and_split "*extenddftf2_internal" - [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r") - (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rm"))) - (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))] + [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,ws,d,&d,r") + (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,md,rm"))) + (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,j,m,d,n"))] "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" |