gcc/ChangeLog:

2017-03-01  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	PR target/79395
	* config/rs6000/altivec.h (vec_ctz and others): Change the
	preprocessor macro that controls conditional compilation from
	_ARCH_PWR9 to __POWER9_VECTOR__.
	(vec_all_ne): Change parameterization of __altivec_scalar_pred
	macro expansion under preprocessor #ifdef __POWER9_VECTOR__
	control (instead of _ARCH_PWR9 control) so that template
	definition uses power9-specific function.
	(vec_any_eq): Likewise.
	(vec_all_ne): Change macro definition to use a power9-specific
	expansion under #ifdef __POWER9_VECTOR__ control (instead of
	_ARCH_PWR9 control).
	(vec_any_eq) Likewise.
	* config/rs6000/rs6000-builtin.def (CMPNEF): Remove BU_P9V_AV_2
	expansion for CMPNEF to remove support for xvcmpnesp instruction.
	(CMPNED): Remove BU_P9V_AV2 expansion for CMPNED to remove
	support for xvcmpnedp instruction.
	(VCMPNEB_P): Replace BU_P9V_AV_P macro expansion with BU_P9V_AV_2
	macro expansion so that Power9 implementation of vec_all_ne does
	not use the AltiVec predicate framework.
	(VCMPNEH_P): Likewise.
	(VCMPNEW_P): Likewise.
	(VCMPNED_P): Likewise.
	(VCMPNEFP_P): Likewise.
	(VCMPNEDP_P): Likewise.
	(VCMPAEB_P): Add BU_P9V_AV_2 macro expansion to change
	implementation of vec_any_eq to not use AltiVec predicate
	framework.
	(VCMPAEH_P): Likewise.
	(VCMPAEW_P): Likewise.
	(VCMPAED_P): Likewise.
	(VCMPAEFP_P): Likewise.
	(VCMPAEDP_P): Likewise.
	(VCMPNE_P): Replace BU_P9V_OVERLOAD_P macro expansion with
	BU_P9V_OVERLOAD_2 so that Power9 implementation of vec_all_ne does
	not use the AltiVec predicate framework.
	(VCMPAE_P): Add BU_P9V_OVERLOAD_2 macro to change implementation
	of vec_any_eq to not use AltiVec predicate framework.
	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Add
	support for predefined __POWER9_VECTOR__ macro to indicate that
	Power9 instruction selection is enabled.
	(altivec_overloaded_builtins): Remove extraneous
	ALTIVEC_BUILTIN_VEC_CMPNE entry for overloaded
	function argument types RS6000_BTI_bool_V16QI and
	RS6000_BTI_bool_V16QI.  Remove erroneous ALTIVEC_BUILTIN_VEC_CMPNE
	entry for overloaded function argument types RS6000_BTI_bool_V4SI
	andRS6000_BTI_bool_V4SI, mapping to P9V_BUILTIN_CMPNEB.  Remove
	two entries mapping to P9V_BUITIN_CMPNED and one entry mapping to
	P9V_BUILTIN_CMPNEF to force use of instructions not specific to
	Power9 for implementations of vec_cmpne.  Change the signature for
	all definitions of the overloaded P9V_BUILTIN_VEC_CMPNE_P function
	(representing vec_all_ne) to remove the previously described first
	argument of type RS6000_BTI_INTSI, as this was an artifact of
	reliance on the AltiVec predicate framework, which is no longer
	used in the implementation of these functions.  Add
	P9V_BUILTIN_VEC_VCMPAE_P entries (representing the vec_anyeq
	function) to match all of the P9V_BUILTIN_VEC_VCMNE_P entries
	since, unlike the AltiVec predicate framework implementation, we
	do not share function descriptors between vec_alle and vec_anyeq.
	(altivec_resolve_overloaded_builtin): Add SFmode and DFmode to the
	set of modes that receive special treatment even when
	TARGET_P9_VECTOR is true.  The special treatment emits code that
	does not depend on Power9 instructions.
	* config/rs6000/vector.md (vector_ne_<mode>_p): Change this
	define_expand to not rely on AltiVec predicate framework.
	(vector_ae_<mode>p): New define_expand to represent vec_any_eq
	function.
	(vector_ne_v2di_p): Change this define_expand to not rely on
	AltiVec predicate framework.
	(vector_ae_v2di_p): New define_expand to represent vec_any_eq
	function.
	(vector_ne_<mode>_p): Change this define_expand to not rely on
	AltiVec predicate framework.
	(vector_ae_<mode>p): New define_expand to represent vec_any_eq
	function.
	* config/rs6000/vsx.md (*vsx_ne_<mode>_p): For modes VSX_EXTRACT_I
	(V16QI, V8HI, V4SI), correct a typo in the code emitted for this
	define_insn pattern.
	(*vsx_ne_<mode>_p): For modes VSX_F (V4SF and V2DF), remove this
	define_insn pattern because the xvcmpne<VSs>. instruction is not
	supported.
	(vcmpne<VSs>): Remove this define_insn because xvcmpne<VSs>
	instruction is not supported.

gcc/testsuite/ChangeLog:

2017-03-01  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	PR target/79395
	* gcc.target/powerpc/vsu/vec-all-ne-10.c: Change scan-assembler
	pattern to look for vcmpequd. instead of vcmpnew.
	* gcc.target/powerpc/vsu/vec-all-ne-14.c: Likewise.
	* gcc.target/powerpc/vsu/vec-all-ne-7.c: Change scan-assembler
	pattern to look for xvcmpeqsp. instead of xvcmpnesp.
	* gcc.target/powerpc/vsu/vec-all-ne-8.c: Change scan-assembler to
	look for xvcmpeqdp. instead of xvcmpnedp.
	* gcc.target/powerpc/vsu/vec-all-ne-9.c: Change scan-assembler to
	look for vcmpequd. instead of vcmpnew.
	* gcc.target/powerpc/vsu/vec-any-eq-10.c: Likewise.
	* gcc.target/powerpc/vsu/vec-any-eq-14.c: Likewise.
	* gcc.target/powerpc/vsu/vec-any-eq-7.c: Change scan-assembler to
	look for xvcmpeqsp. instead of xvcmpnesp.
	* gcc.target/powerpc/vsu/vec-any-eq-8.c: Change scan-assembler to
	look for xvcmpeqdp. instead of xvcmpnedp.
	* gcc.target/powerpc/vsu/vec-any-eq-9.c: Change scan-assembler to
	look for vcmpequd. instead of vcmpnew.
	* gcc.target/powerpc/vsu/vec-cmpne-8.c: Change scan-assembler to
	look for vcmpeqsp instead of xvcmpnesp.
	* gcc.target/powerpc/vsu/vec-cmpne-9.c: Change scan-assembler to
	look for xvcmpeqdp instead of xvcmpnedp.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@245811 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 310 insertions, 146 deletions

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 53ddced016f..cd4b724bc52 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -390,7 +390,7 @@
 #define vec_vupklsw __builtin_vec_vupklsw
 #endif
 
-#ifdef _ARCH_PWR9
+#ifdef __POWER9_VECTOR__
 /* Vector additions added in ISA 3.0.  */
 #define vec_vctz __builtin_vec_vctz
 #define vec_cnttz __builtin_vec_vctz
@@ -510,7 +510,7 @@ __altivec_unary_pred(vec_any_numeric,
 __altivec_scalar_pred(vec_all_eq,
   __builtin_vec_vcmpeq_p (__CR6_LT, a1, a2))
 
-#ifndef _ARCH_PWR9
+#ifndef __POWER9_VECTOR__
 __altivec_scalar_pred(vec_all_ne,
   __builtin_vec_vcmpeq_p (__CR6_EQ, a1, a2))
 __altivec_scalar_pred(vec_any_eq,
@@ -521,9 +521,9 @@ __altivec_scalar_pred(vec_all_nez,
 __altivec_scalar_pred(vec_any_eqz,
   __builtin_vec_vcmpnez_p (__CR6_LT_REV, a1, a2))
 __altivec_scalar_pred(vec_all_ne,
-  __builtin_vec_vcmpne_p (__CR6_LT, a1, a2))
+  __builtin_vec_allne_p (a1, a2))
 __altivec_scalar_pred(vec_any_eq,
-  __builtin_vec_vcmpne_p (__CR6_LT_REV, a1, a2))
+  __builtin_vec_anyeq_p (a1, a2))
 #endif
 
 __altivec_scalar_pred(vec_any_ne,
@@ -586,11 +586,11 @@ __altivec_scalar_pred(vec_any_nle,
 
 #define vec_all_eq(a1, a2) __builtin_vec_vcmpeq_p (__CR6_LT, (a1), (a2))
 
-#ifdef _ARCH_PWR9
+#ifdef __POWER9_VECTOR__
 #define vec_all_nez(a1, a2) __builtin_vec_vcmpnez_p (__CR6_LT, (a1), (a2))
 #define vec_any_eqz(a1, a2) __builtin_vec_vcmpnez_p (__CR6_LT_REV, (a1), (a2))
-#define vec_all_ne(a1, a2) __builtin_vec_vcmpne_p (__CR6_LT, (a1), (a2))
-#define vec_any_eq(a1, a2) __builtin_vec_vcmpne_p (__CR6_LT_REV, (a1), (a2))
+#define vec_all_ne(a1, a2) __builtin_vec_vcmpne_p ((a1), (a2))
+#define vec_any_eq(a1, a2) __builtin_vec_vcmpae_p ((a1), (a2))
 #else
 #define vec_all_ne(a1, a2) __builtin_vec_vcmpeq_p (__CR6_EQ, (a1), (a2))
 #define vec_any_eq(a1, a2) __builtin_vec_vcmpeq_p (__CR6_EQ_REV, (a1), (a2))
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 61aed2ba98a..9c856424c8d 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -2053,24 +2053,27 @@ BU_P9V_AV_1 (VCTZLSBB, "vctzlsbb",		CONST,	vctzlsbb)
    new awareness of the "vector compare not equal" (vcmpneb, vcmpneb.,
    vcmpneh, vcmpneh., vcmpnew, vcmpnew.) and "vector compare
    not equal or zero" (vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
-   vcmpnezw, vcmpnezw.) instructions.  For consistency with existing
-   infrastructure, this new awareness is integrated in the style of
-   earlier implementations of the __builtin_vec_cmpne and
-   __builtin_vec_cmpeq_p functions. */
+   vcmpnezw, vcmpnezw.) instructions.  */
 
 BU_P9V_AV_2 (CMPNEB,	"vcmpneb",	CONST,	vcmpneb)
 BU_P9V_AV_2 (CMPNEH,	"vcmpneh",	CONST,	vcmpneh)
 BU_P9V_AV_2 (CMPNEW,	"vcmpnew",	CONST,	vcmpnew)
-BU_P9V_AV_2 (CMPNEF,	"vcmpnef",	CONST,	vcmpnesp)
-BU_P9V_AV_2 (CMPNED,	"vcmpned",	CONST,	vcmpnedp)
 
-BU_P9V_AV_P (VCMPNEB_P,	"vcmpneb_p",	CONST,	vector_ne_v16qi_p)
-BU_P9V_AV_P (VCMPNEH_P,	"vcmpneh_p",	CONST,	vector_ne_v8hi_p)
-BU_P9V_AV_P (VCMPNEW_P,	"vcmpnew_p",	CONST,	vector_ne_v4si_p)
-BU_P9V_AV_P (VCMPNED_P,	"vcmpned_p",	CONST,	vector_ne_v2di_p)
+BU_P9V_AV_2 (VCMPNEB_P,	"vcmpneb_p",	CONST,	vector_ne_v16qi_p)
+BU_P9V_AV_2 (VCMPNEH_P,	"vcmpneh_p",	CONST,	vector_ne_v8hi_p)
+BU_P9V_AV_2 (VCMPNEW_P,	"vcmpnew_p",	CONST,	vector_ne_v4si_p)
+BU_P9V_AV_2 (VCMPNED_P,	"vcmpned_p",	CONST,	vector_ne_v2di_p)
 
-BU_P9V_AV_P (VCMPNEFP_P,	"vcmpnefp_p",	CONST,	vector_ne_v4sf_p)
-BU_P9V_AV_P (VCMPNEDP_P,	"vcmpnedp_p",	CONST,	vector_ne_v2df_p)
+BU_P9V_AV_2 (VCMPNEFP_P,	"vcmpnefp_p",	CONST,	vector_ne_v4sf_p)
+BU_P9V_AV_2 (VCMPNEDP_P,	"vcmpnedp_p",	CONST,	vector_ne_v2df_p)
+
+BU_P9V_AV_2 (VCMPAEB_P,	"vcmpaeb_p",	CONST,	vector_ae_v16qi_p)
+BU_P9V_AV_2 (VCMPAEH_P,	"vcmpaeh_p",	CONST,	vector_ae_v8hi_p)
+BU_P9V_AV_2 (VCMPAEW_P,	"vcmpaew_p",	CONST,	vector_ae_v4si_p)
+BU_P9V_AV_2 (VCMPAED_P,	"vcmpaed_p",	CONST,	vector_ae_v2di_p)
+
+BU_P9V_AV_2 (VCMPAEFP_P,	"vcmpaefp_p",	CONST,	vector_ae_v4sf_p)
+BU_P9V_AV_2 (VCMPAEDP_P,	"vcmpaedp_p",	CONST,	vector_ae_v2df_p)
 
 BU_P9V_AV_2 (CMPNEZB,	"vcmpnezb",	CONST,	vcmpnezb)
 BU_P9V_AV_2 (CMPNEZH,	"vcmpnezh",	CONST,	vcmpnezh)
@@ -2095,7 +2098,8 @@ BU_P9V_OVERLOAD_3 (VINSERT4B,	"vinsert4b")
 BU_P9V_OVERLOAD_2 (CMPNEZ,	"vcmpnez")
 
 BU_P9V_OVERLOAD_P (VCMPNEZ_P,	"vcmpnez_p")
-BU_P9V_OVERLOAD_P (VCMPNE_P,	"vcmpne_p")
+BU_P9V_OVERLOAD_2 (VCMPNE_P,	"vcmpne_p")
+BU_P9V_OVERLOAD_2 (VCMPAE_P,	"vcmpae_p")
 
 /* ISA 3.0 Vector scalar overloaded 1 argument functions */
 BU_P9V_OVERLOAD_1 (VCLZLSBB,	"vclzlsbb")
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 20c17f0e787..0ab71a6c9e0 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -391,6 +391,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
     }
   if ((flags & OPTION_MASK_P8_VECTOR) != 0)
     rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
+  if ((flags & OPTION_MASK_P9_VECTOR) != 0)
+    rs6000_define_or_undefine_macro (define_p, "__POWER9_VECTOR__");
   if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
     rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");
   if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
@@ -4544,9 +4546,6 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
     RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
-    RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
-    RS6000_BTI_bool_V16QI, 0 },
-  { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
     RS6000_BTI_unsigned_V16QI, 0 },
 
@@ -4569,119 +4568,216 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
     RS6000_BTI_unsigned_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
-    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
-    RS6000_BTI_bool_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNED,
-    RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
-  { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEF,
-    RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-  { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNED,
-    RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
 
   /* The following 2 entries have been deprecated.  */
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
-    RS6000_BTI_unsigned_V16QI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
+    RS6000_BTI_unsigned_V16QI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
-    RS6000_BTI_bool_V16QI },
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
+    RS6000_BTI_bool_V16QI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
-    RS6000_BTI_unsigned_V16QI },
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
+    RS6000_BTI_unsigned_V16QI, 0 },
 
   /* The following 2 entries have been deprecated.  */
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
-    RS6000_BTI_V16QI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
+    RS6000_BTI_V16QI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI,
-    RS6000_BTI_bool_V16QI },
+    RS6000_BTI_INTSI, RS6000_BTI_V16QI,
+    RS6000_BTI_bool_V16QI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
+    RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
-    RS6000_BTI_bool_V16QI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
+    RS6000_BTI_bool_V16QI, 0 },
 
   /* The following 2 entries have been deprecated.  */
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
-    RS6000_BTI_unsigned_V8HI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
+    RS6000_BTI_unsigned_V8HI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
-    RS6000_BTI_bool_V8HI },
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
+    RS6000_BTI_bool_V8HI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
-    RS6000_BTI_unsigned_V8HI },
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
+    RS6000_BTI_unsigned_V8HI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
+    RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
 
   /* The following 2 entries have been deprecated.  */
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
-    RS6000_BTI_V8HI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
+    RS6000_BTI_V8HI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI,
-    RS6000_BTI_bool_V8HI },
+    RS6000_BTI_INTSI, RS6000_BTI_V8HI,
+    RS6000_BTI_bool_V8HI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
-    RS6000_BTI_bool_V8HI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
+    RS6000_BTI_bool_V8HI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
-    RS6000_BTI_pixel_V8HI },
+    RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
+    RS6000_BTI_pixel_V8HI, 0 },
 
   /* The following 2 entries have been deprecated.  */
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
-    RS6000_BTI_unsigned_V4SI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
+    RS6000_BTI_unsigned_V4SI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
-    RS6000_BTI_bool_V4SI },
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
+    RS6000_BTI_bool_V4SI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
-    RS6000_BTI_unsigned_V4SI },
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
+    RS6000_BTI_unsigned_V4SI, 0 },
 
   /* The following 2 entries have been deprecated.  */
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
-    RS6000_BTI_V4SI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
+    RS6000_BTI_V4SI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI,
-    RS6000_BTI_bool_V4SI },
+    RS6000_BTI_INTSI, RS6000_BTI_V4SI,
+    RS6000_BTI_bool_V4SI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
+    RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
-    RS6000_BTI_bool_V4SI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
+    RS6000_BTI_bool_V4SI, 0 },
 
   /* The following 2 entries have been deprecated.  */
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
-    RS6000_BTI_unsigned_V2DI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
+    RS6000_BTI_unsigned_V2DI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
-      RS6000_BTI_bool_V2DI },
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
+    RS6000_BTI_bool_V2DI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
-    RS6000_BTI_unsigned_V2DI },
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
+    RS6000_BTI_unsigned_V2DI, 0
+  },
 
   /* The following 2 entries have been deprecated.  */
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
-    RS6000_BTI_V2DI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
+    RS6000_BTI_V2DI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI,
-    RS6000_BTI_bool_V2DI },
+    RS6000_BTI_INTSI, RS6000_BTI_V2DI,
+    RS6000_BTI_bool_V2DI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
+    RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
-    RS6000_BTI_bool_V2DI },
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
+    RS6000_BTI_bool_V2DI, 0 },
 
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
+    RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
+    RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
+
+  /* The following 2 entries have been deprecated.  */
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
+    RS6000_BTI_unsigned_V16QI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
+    RS6000_BTI_bool_V16QI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
+    RS6000_BTI_unsigned_V16QI, 0 },
+
+  /* The following 2 entries have been deprecated.  */
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
+    RS6000_BTI_V16QI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
+    RS6000_BTI_INTSI, RS6000_BTI_V16QI,
+    RS6000_BTI_bool_V16QI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
+    RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
+    RS6000_BTI_bool_V16QI, 0 },
+
+  /* The following 2 entries have been deprecated.  */
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
+    RS6000_BTI_unsigned_V8HI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
+    RS6000_BTI_bool_V8HI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
+    RS6000_BTI_unsigned_V8HI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
+    RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
+
+  /* The following 2 entries have been deprecated.  */
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
+    RS6000_BTI_V8HI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
+    RS6000_BTI_INTSI, RS6000_BTI_V8HI,
+    RS6000_BTI_bool_V8HI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
+    RS6000_BTI_bool_V8HI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
+    RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
+    RS6000_BTI_pixel_V8HI, 0 },
+
+  /* The following 2 entries have been deprecated.  */
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
+    RS6000_BTI_unsigned_V4SI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
+    RS6000_BTI_bool_V4SI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
+    RS6000_BTI_unsigned_V4SI, 0 },
+
+  /* The following 2 entries have been deprecated.  */
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
+    RS6000_BTI_V4SI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
+    RS6000_BTI_INTSI, RS6000_BTI_V4SI,
+    RS6000_BTI_bool_V4SI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
+    RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
+    RS6000_BTI_bool_V4SI, 0 },
+
+  /* The following 2 entries have been deprecated.  */
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
+    RS6000_BTI_unsigned_V2DI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
+    RS6000_BTI_bool_V2DI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
+    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
+    RS6000_BTI_unsigned_V2DI, 0
+  },
+
+  /* The following 2 entries have been deprecated.  */
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
+    RS6000_BTI_V2DI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
+    RS6000_BTI_INTSI, RS6000_BTI_V2DI,
+    RS6000_BTI_bool_V2DI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
+    RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
+    RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
+    RS6000_BTI_bool_V2DI, 0 },
+
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
+    RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
+  { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
+    RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
 
   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
@@ -5339,10 +5435,13 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
       tree arg1_type = TREE_TYPE (arg1);
 
       /* Power9 instructions provide the most efficient implementation of
-	 ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode.  */
+	 ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode
+	 or SFmode or DFmode.  */
       if (!TARGET_P9_VECTOR
 	  || (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode)
-	  || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode))
+	  || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode)
+	  || (TYPE_MODE (TREE_TYPE (arg0_type)) == SFmode)
+	  || (TYPE_MODE (TREE_TYPE (arg0_type)) == DFmode))
 	{
 	  /* Both arguments must be vectors and the types must match.  */
 	  if (arg0_type != arg1_type)
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 8f571739d30..ef6bd14b2b1 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -693,19 +693,45 @@
   "")
 
 ;; This expansion handles the V16QI, V8HI, and V4SI modes in the
-;; implementation of the vec_all_ne and vec_any_eq built-in functions
-;; on Power9.
+;; implementation of the vec_all_ne built-in functions on Power9.
 (define_expand "vector_ne_<mode>_p"
   [(parallel
     [(set (reg:CC CR6_REGNO)
 	  (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand")
 			     (match_operand:VI 2 "vlogical_operand"))]
 	   UNSPEC_PREDICATE))
-     (set (match_operand:VI 0 "vlogical_operand")
+     (set (match_dup 4)
 	  (ne:VI (match_dup 1)
-		 (match_dup 2)))])]
+		 (match_dup 2)))])
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(lt:SI (reg:CC CR6_REGNO)
+	       (const_int 0)))]
   "TARGET_P9_VECTOR"
-  "")
+{
+  operands[4] = gen_reg_rtx (<MODE>mode);
+})
+
+;; This expansion handles the V16QI, V8HI, and V4SI modes in the
+;; implementation of the vec_any_eq built-in functions on Power9.
+(define_expand "vector_ae_<mode>_p"
+  [(parallel
+    [(set (reg:CC CR6_REGNO)
+	  (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand")
+			     (match_operand:VI 2 "vlogical_operand"))]
+	   UNSPEC_PREDICATE))
+     (set (match_dup 4)
+	  (ne:VI (match_dup 1)
+		 (match_dup 2)))])
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(lt:SI (reg:CC CR6_REGNO)
+	       (const_int 0)))
+   (set (match_dup 0)
+	(xor:SI (match_dup 0)
+		(const_int 1)))]
+  "TARGET_P9_VECTOR"
+{
+  operands[4] = gen_reg_rtx (<MODE>mode);
+})
 
 ;; This expansion handles the V16QI, V8HI, and V4SI modes in the
 ;; implementation of the vec_all_nez and vec_any_eqz built-in
@@ -725,41 +751,101 @@
   "TARGET_P9_VECTOR"
   "")
 
-;; This expansion handles the V4DI mode in the implementation of the
-;; vec_all_ne and vec_any_eq built-in function on Power9.
+;; This expansion handles the V2DI mode in the implementation of the
+;; vec_all_ne built-in function on Power9.
 ;;
-;; Since the "xvcmpne<mode>." instruction does not support DImode,
-;; we'll use a V4SI comparison, which will set the values of the CR6
-;; flags to be the same as if we had performed a DImode comparison.
-;; (All of the entries in a V2DI vector are not equal iff all of the
-;; entries in the same vector, interpeted as V4SI are not equal, and
-;; likewise in the test for "any equal".)
+;; Since the Power9 "xvcmpne<mode>." instruction does not support DImode,
+;; this expands into the same rtl that would be used for the Power8
+;; architecture.
 (define_expand "vector_ne_v2di_p"
   [(parallel
     [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(ne:CC (match_operand:V4SI 1 "vlogical_operand")
-			     (match_operand:V4SI 2 "vlogical_operand"))]
-	   UNSPEC_PREDICATE))
-     (set (match_operand:V4SI 0 "vlogical_operand")
-	  (ne:V4SI (match_dup 1)
-		   (match_dup 2)))])]
+	  (unspec:CC [(eq:CC (match_operand:V2DI 1 "vlogical_operand")
+			     (match_operand:V2DI 2 "vlogical_operand"))]
+		     UNSPEC_PREDICATE))
+     (set (match_dup 4)
+	  (eq:V2DI (match_dup 1)
+		   (match_dup 2)))])
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(eq:SI (reg:CC CR6_REGNO)
+	       (const_int 0)))]
   "TARGET_P9_VECTOR"
-  "")
+{
+  operands[4] = gen_reg_rtx (V2DImode);
+})
+
+;; This expansion handles the V2DI mode in the implementation of the
+;; vec_any_eq built-in function on Power9.
+;;
+;; Since the Power9 "xvcmpne<mode>." instruction does not support DImode,
+;; this expands into the same rtl that would be used for the Power8
+;; architecture.
+(define_expand "vector_ae_v2di_p"
+  [(parallel
+    [(set (reg:CC CR6_REGNO)
+	  (unspec:CC [(eq:CC (match_operand:V2DI 1 "vlogical_operand")
+			     (match_operand:V2DI 2 "vlogical_operand"))]
+		     UNSPEC_PREDICATE))
+     (set (match_dup 4)
+	  (eq:V2DI (match_dup 1)
+		   (match_dup 2)))])
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(lt:SI (reg:CC CR6_REGNO)
+	       (const_int 0)))
+   (set (match_dup 0)
+	(xor:SI (match_dup 0)
+		(const_int 1)))]
+  "TARGET_P9_VECTOR"
+{
+  operands[4] = gen_reg_rtx (V2DImode);
+})
 
 ;; This expansion handles the V4SF and V2DF modes in the Power9
-;; implementation of the vec_all_ne and vec_any_eq built-in
-;; functions.
+;; implementation of the vec_all_ne built-in functions.  Note that the
+;; expansions for this pattern with these modes makes no use of power9-
+;; specific instructions since there are no new power9 instructions
+;; for vector compare not equal with floating point arguments.
 (define_expand "vector_ne_<mode>_p"
   [(parallel
     [(set (reg:CC CR6_REGNO)
-	  (unspec:CC [(ne:CC (match_operand:VEC_F 1 "vlogical_operand")
+	  (unspec:CC [(eq:CC (match_operand:VEC_F 1 "vlogical_operand")
 			     (match_operand:VEC_F 2 "vlogical_operand"))]
-	   UNSPEC_PREDICATE))
-     (set (match_operand:VEC_F 0 "vlogical_operand")
-	  (ne:VEC_F (match_dup 1)
-		    (match_dup 2)))])]
+		     UNSPEC_PREDICATE))
+     (set (match_dup 4)
+	  (eq:VEC_F (match_dup 1)
+		    (match_dup 2)))])
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(eq:SI (reg:CC CR6_REGNO)
+	       (const_int 0)))]
   "TARGET_P9_VECTOR"
-  "")
+{
+  operands[4] = gen_reg_rtx (<MODE>mode);
+})
+
+;; This expansion handles the V4SF and V2DF modes in the Power9
+;; implementation of the vec_any_eq built-in functions.  Note that the
+;; expansions for this pattern with these modes makes no use of power9-
+;; specific instructions since there are no new power9 instructions
+;; for vector compare not equal with floating point arguments.
+(define_expand "vector_ae_<mode>_p"
+  [(parallel
+    [(set (reg:CC CR6_REGNO)
+	  (unspec:CC [(eq:CC (match_operand:VEC_F 1 "vlogical_operand")
+			     (match_operand:VEC_F 2 "vlogical_operand"))]
+		     UNSPEC_PREDICATE))
+     (set (match_dup 4)
+	  (eq:VEC_F (match_dup 1)
+		    (match_dup 2)))])
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(lt:SI (reg:CC CR6_REGNO)
+	       (const_int 0)))
+   (set (match_dup 0)
+	(xor:SI (match_dup 0)
+		(const_int 1)))]
+  "TARGET_P9_VECTOR"
+{
+  operands[4] = gen_reg_rtx (<MODE>mode);
+})
 
 (define_expand "vector_gt_<mode>_p"
   [(parallel
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d1907948877..111c2e8214b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3596,7 +3596,8 @@
 ;; Compare vectors producing a vector result and a predicate, setting CR6
 ;; to indicate a combined status.  This pattern matches v16qi, v8hi, and
 ;; v4si modes.  It does not match v2df, v4sf, or v2di modes.  There's no
-;; need to match the v2di mode because that is expanded into v4si.
+;; need to match v4sf, v2df, or v2di modes because those are expanded
+;; to use Power8 instructions.
 (define_insn "*vsx_ne_<mode>_p"
   [(set (reg:CC CR6_REGNO)
 	(unspec:CC
@@ -3607,22 +3608,7 @@
 	(ne:VSX_EXTRACT_I (match_dup 1)
 			  (match_dup 2)))]
   "TARGET_P9_VECTOR"
-  "xvcmpne<VSX_EXTRACT_WIDTH>. %0,%1,%2"
-  [(set_attr "type" "vecsimple")])
-
-;; Compare vectors producing a vector result and a predicate, setting CR6
-;; to indicate a combined status, for v4sf and v2df operands.
-(define_insn "*vsx_ne_<mode>_p"
-  [(set (reg:CC CR6_REGNO)
-	(unspec:CC [(ne:CC
-		     (match_operand:VSX_F 1 "vsx_register_operand" "wa")
-		     (match_operand:VSX_F 2 "vsx_register_operand" "wa"))]
-	 UNSPEC_PREDICATE))
-   (set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
-	(ne:VSX_F (match_dup 1)
-		  (match_dup 2)))]
-  "TARGET_P9_VECTOR"
-  "xvcmpne<VSs>. %x0,%x1,%x2"
+  "vcmpne<VSX_EXTRACT_WIDTH>. %0,%1,%2"
   [(set_attr "type" "vecsimple")])
 
 (define_insn "*vector_nez_<mode>_p"
@@ -3742,17 +3728,6 @@
   "vcmpnew %0,%1,%2"
   [(set_attr "type" "vecsimple")])
 
-;; Vector Compare Not Equal Float or Double
-(define_insn "vcmpne<VSs>"
-  [(set (match_operand:<VSI> 0 "vsx_register_operand" "=wa")
-	(unspec:<VSI>
-	 [(match_operand:VSX_F 1 "vsx_register_operand" "wa")
-	  (match_operand:VSX_F 2 "vsx_register_operand" "wa")]
-	 UNSPEC_VCMPNEH))]
-  "TARGET_P9_VECTOR"
-  "xvcmpne<VSs> %x0,%x1,%x2"
-  [(set_attr "type" "vecsimple")])
-
 ;; Vector Compare Not Equal or Zero Word
 (define_insn "vcmpnezw"
   [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")