* config/rx/rx-modes.def: New file.

        * config/rx/rx.h (FIRST_PSEUDO_REGISTER): Increase to 17.
        (CC_REGNUM): Define.
        (FIXED_REGISTERS, CALL_USED_REGISTERS, REGISTER_NAMES): Add cc
        register.
        (CC_NO_CARRY, NOTICE_UPDATE_CC): Delete.
        (SELECT_CC_MODE): Define.
        * config/rx/rx.md (CC_REG): Define.  Update all patterns to use
        (reg:CC CC_REG) instead of (cc0).
        (attr "cc"): Delete.
        (cbranchsi4): Do not split compare and branch here. Instead move
        it to...
        (cbranchsi4_<code>): ... here.  New patterns.
        (cmpsi): Call rx-compare_redundant to find out if it is necessary
        to emit the compare instruction.
        * config/rx/rx.c (rx_gen-cond_branch_template): Remove tests of
        cc_status flags.
        (rx_get_stack_layout): Iterate up to before CC_REGNUM not
        FIRST_PSEUDO_REGNUM.
        (rx_expand_prologue, rx_expand_epilogue): Likewise.
        (rx_notice_update_cc): Delete.
        (rx_cc_modes_compatible): New function.
        (flags_needed_for_conditional): New function.
        (flags_from_mode): New function.
        (rx_compare_redundant): New function - scans backwards through
        insn list to find out if condition flags are already set
        correctly.
        (TARGET_CC_MODES_COMPATIBLE): Define.
        * config/rx/rx-protos.h (rx_compare_redundant): Prototype.

        * config/rx/rx.h (BRANCH_COST): Define.
        (REGISTER_MOVE_COST): Define.
        * config/rx/predicates (rx_source_operand): Allow all constant
        types.
        * config/rx/rx.md (addsi3): Add alternative for swapped operands.
        (tstsi4): New pattern.
        * config/rx/rx.c (rx_memory_move_cost): Define.
        (TARGET_MEMORY_MOVE_COST): Define.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161592 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 287 insertions, 245 deletions

diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index 6fe25259472..aeba85ffe39 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -47,6 +47,7 @@
 (define_constants
   [
    (SP_REG 0)
+   (CC_REG 		   16)
 
    (UNSPEC_LOW_REG         0)
    (UNSPEC_HIGH_REG        1)
@@ -86,14 +87,6 @@
   ]
 )
 
-;; Condition code settings:
-;;   none     - insn does not affect the condition code bits
-;;   set_zs   - insn sets z,s to usable values;
-;;   set_zso  - insn sets z,s,o to usable values;
-;;   set_zsoc - insn sets z,s,o,c to usable values;
-;;   clobber  - value of cc0 is unknown
-(define_attr "cc" "none,set_zs,set_zso,set_zsoc,set_zsc,clobber" (const_string "none"))
-
 (define_attr "length" "" (const_int 8))
 
 (include "predicates.md")
@@ -156,77 +149,120 @@
 
 ;; Comparisons
 
+;; Note - we do not specify the two instructions necessary to perform
+;; a compare-and-branch in the cbranchsi4 pattern because that would
+;; allow the comparison to be moved away from the jump before the reload
+;; pass has completed.  That would be problematical because reload can
+;; generate ADDSI3 instructions which would corrupt the PSW flags.
+
 (define_expand "cbranchsi4"
-  [(set (cc0) (compare:CC (match_operand:SI 1 "register_operand")
-			  (match_operand:SI 2 "rx_source_operand")))
-   (set (pc)
-	(if_then_else (match_operator:SI  0 "comparison_operator"
-					  [(cc0) (const_int 0)])
+  [(set (pc)
+	(if_then_else (match_operator:SI 0 "comparison_operator"
+					 [(match_operand:SI 1 "register_operand")
+					  (match_operand:SI 2 "rx_source_operand")])
 		      (label_ref (match_operand 3 ""))
-		      (pc)))]
+		      (pc)))
+   ]
   ""
   ""
 )
 
+(define_insn_and_split "*cbranchsi4_<code>"
+  [(set (pc)
+	(if_then_else (most_cond:SI (match_operand:SI  0 "register_operand"  "r")
+				    (match_operand:SI  1 "rx_source_operand" "riQ"))
+		      (label_ref (match_operand        2 "" ""))
+		      (pc)))
+   ]
+  ""
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "
+  /* We contstruct the split by hand as otherwise the JUMP_LABEL
+     attribute is not set correctly on the jump insn.  */
+  emit_insn (gen_cmpsi (operands[0], operands[1]));
+  
+  emit_jump_insn (gen_conditional_branch (operands[2],
+  		 gen_rtx_fmt_ee (<most_cond:CODE>, CCmode,
+				 gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
+  "
+)
+
 (define_expand "cbranchsf4"
-  [(set (cc0) (compare:CC (match_operand:SF 1 "register_operand")
-			  (match_operand:SF 2 "rx_source_operand")))
-   (set (pc)
-	(if_then_else (match_operator:SI  0 "comparison_operator"
-					  [(cc0) (const_int 0)])
+  [(set (pc)
+	(if_then_else (match_operator:SF 0 "comparison_operator"
+					 [(match_operand:SF 1 "register_operand")
+					  (match_operand:SF 2 "rx_source_operand")])
 		      (label_ref (match_operand 3 ""))
-		      (pc)))]
-  "ALLOW_RX_FPU_INSNS && (cfun == NULL || !cfun->can_throw_non_call_exceptions)"
+		      (pc)))
+   ]
+  "ALLOW_RX_FPU_INSNS"
   ""
 )
 
-;; The TST instruction is not used as it does not set the Carry flag,
-;; so for example, the LessThan comparison cannot be tested.
-;;
-;; (define_insn "tstsi"
-;;   [(set (cc0)
-;;         (match_operand:SI 0 "rx_source_operand"  "r,i,Q")))]
-;;   ""
-;;   {
-;;     rx_float_compare_mode = false;
-;;     return "tst\t%Q0";
-;;   }
-;;   [(set_attr "cc" "set_zs")
-;;    (set_attr "timings" "11,11,33")
-;;    (set_attr "length" "3,7,6")]
-;; )
+(define_insn_and_split "*cbranchsf4_<code>"
+  [(set (pc)
+	(if_then_else (most_cond:SF (match_operand:SF  0 "register_operand"  "r")
+				    (match_operand:SF  1 "rx_source_operand" "rFiQ"))
+		      (label_ref (match_operand        2 "" ""))
+		      (pc)))
+   ]
+  "ALLOW_RX_FPU_INSNS"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+  "
+  /* We contstruct the split by hand as otherwise the JUMP_LABEL
+     attribute is not set correctly on the jump insn.  */
+  emit_insn (gen_cmpsf (operands[0], operands[1]));
+  
+  emit_jump_insn (gen_conditional_branch (operands[2],
+  		 gen_rtx_fmt_ee (<most_cond:CODE>, CCmode,
+ 		 		 gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
+  "
+)
+
+(define_insn "tstsi"
+  [(set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (and:SI (match_operand:SI 0 "register_operand"  "r,r,r")
+			       (match_operand:SI 1 "rx_source_operand" "r,i,Q"))
+		       (const_int 0)))]
+  ""
+  {
+    rx_float_compare_mode = false;
+    return "tst\t%Q1, %0";
+  }
+  [(set_attr "timings" "11,11,33")
+   (set_attr "length"   "3,7,6")]
+)
 
 (define_insn "cmpsi"
-  [(set (cc0) (compare:CC
-	       (match_operand:SI 0 "register_operand"  "r,r,r,r,r,r,r")
-	       (match_operand:SI 1 "rx_source_operand"
-				 "r,Uint04,Int08,Sint16,Sint24,i,Q")))]
+  [(set (reg:CC CC_REG)
+	(compare:CC (match_operand:SI 0 "register_operand"  "r,r,r,r,r,r,r")
+		    (match_operand:SI 1 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")))]
   ""
   {
     rx_float_compare_mode = false;
+    if (rx_compare_redundant (insn))
+      return "; Compare Eliminated: cmp %Q1, %0";
     return "cmp\t%Q1, %0";
   }
-  [(set_attr "cc" "set_zsoc")
-   (set_attr "timings" "11,11,11,11,11,11,33")
+  [(set_attr "timings" "11,11,11,11,11,11,33")
    (set_attr "length"  "2,2,3,4,5,6,5")]
 )
 
-;; This pattern is disabled if the function can throw non-call exceptions,
-;; because it could generate a floating point exception, which would
-;; introduce an edge into the flow graph between this insn and the
-;; conditional branch insn to follow, thus breaking the cc0 relationship.
-;; Run the g++ test g++.dg/eh/080514-1.C to see this happen.
+;; ??? g++.dg/eh/080514-1.C to see this happen.
 (define_insn "cmpsf"
-  [(set (cc0)
-	(compare:CC (match_operand:SF 0 "register_operand"  "r,r,r")
-		    (match_operand:SF 1 "rx_source_operand" "r,i,Q")))]
-  "ALLOW_RX_FPU_INSNS && (cfun == NULL || !cfun->can_throw_non_call_exceptions)"
+  [(set (reg:CC_ZSO CC_REG)
+	(compare:CC_ZSO (match_operand:SF 0 "register_operand"  "r,r,r")
+			(match_operand:SF 1 "rx_source_operand" "r,iF,Q")))]
+  "ALLOW_RX_FPU_INSNS"
   {
     rx_float_compare_mode = true;
     return "fcmp\t%1, %0";
   }
-  [(set_attr "cc" "set_zso")
-   (set_attr "timings" "11,11,33")
+  [(set_attr "timings" "11,11,33")
    (set_attr "length" "3,7,5")]
 )
 
@@ -234,17 +270,17 @@
 
 (define_expand "b<code>"
   [(set (pc)
-        (if_then_else (most_cond (cc0) (const_int 0))
+        (if_then_else (most_cond (reg:CC CC_REG) (const_int 0))
                       (label_ref (match_operand 0))
                       (pc)))]
   ""
   ""
 )
 
-(define_insn "*conditional_branch"
+(define_insn "conditional_branch"
   [(set (pc)
 	(if_then_else (match_operator           1 "comparison_operator"
-						[(cc0) (const_int 0)])
+						[(reg:CC CC_REG) (const_int 0)])
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
@@ -253,14 +289,13 @@
   }
   [(set_attr "length" "8")    ;; This length is wrong, but it is
                               ;; too hard to compute statically.
-   (set_attr "timings" "33")  ;; The timing assumes that the branch is taken.
-   (set_attr "cc" "clobber")] ;; FIXME: This clobber is wrong.
+   (set_attr "timings" "33")] ;; The timing assumes that the branch is taken.
 )
 
 (define_insn "*reveresed_conditional_branch"
   [(set (pc)
 	(if_then_else (match_operator 1 "comparison_operator"
-				      [(cc0) (const_int 0)])
+				      [(reg:CC CC_REG) (const_int 0)])
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
@@ -269,38 +304,37 @@
   }
   [(set_attr "length" "8")    ;; This length is wrong, but it is
                               ;; too hard to compute statically.
-   (set_attr "timings" "33")  ;; The timing assumes that the branch is taken.
-   (set_attr "cc" "clobber")] ;; FIXME: This clobber is wrong.
+   (set_attr "timings" "33")] ;; The timing assumes that the branch is taken.
 )
 
 (define_insn "jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))]
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
   ""
   "bra\t%0"
   [(set_attr "length" "4")
-   (set_attr "timings" "33")
-   (set_attr "cc" "clobber")] ;; FIXME: This clobber is wrong.
+   (set_attr "timings" "33")]
 )
 
 (define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
+  [(set (pc)
+	(match_operand:SI 0 "register_operand" "r"))]
   ""
   "jmp\t%0"
   [(set_attr "length" "2")
-   (set_attr "timings" "33")
-   (set_attr "cc" "clobber")] ;; FIXME: This clobber is wrong.
+   (set_attr "timings" "33")]
 )
 
 (define_insn "tablejump"
-  [(set (pc) (match_operand:SI     0 "register_operand" "r"))
+  [(set (pc)
+	(match_operand:SI          0 "register_operand" "r"))
    (use (label_ref (match_operand  1 "" "")))]
   ""
   { return flag_pic ? (TARGET_AS100_SYNTAX ? "\n?:\tbra\t%0"
 					   : "\n1:\tbra\t%0")
 	                                   : "jmp\t%0";
   }
-  [(set_attr "cc" "clobber") ;; FIXME: This clobber is wrong.
-   (set_attr "timings" "33")
+  [(set_attr "timings" "33")
    (set_attr "length" "2")]
 )
 
@@ -324,11 +358,10 @@
 )
 
 (define_insn "pop_and_return"
-  [(match_parallel                    1 "rx_rtsd_vector"
+  [(match_parallel 1 "rx_rtsd_vector"
 		   [(set:SI (reg:SI SP_REG)
 			    (plus:SI (reg:SI SP_REG)
-				     (match_operand:SI
-				      0 "const_int_operand" "n")))])]
+				     (match_operand:SI 0 "const_int_operand" "n")))])]
   "reload_completed"
   {
     rx_emit_stack_popm (operands, false);
@@ -385,13 +418,13 @@
 
 (define_insn "call_internal"
   [(call (mem:QI (match_operand:SI 0 "rx_call_operand" "r,Symbol"))
-	 (match_operand:SI         1 "general_operand" "g,g"))]
+	 (match_operand:SI         1 "general_operand" "g,g"))
+   (clobber (reg:CC CC_REG))]
   ""
   "@
   jsr\t%0
   bsr\t%A0"
   [(set_attr "length" "2,4")
-   (set_attr "cc" "clobber")
    (set_attr "timings" "33")]
 )
 
@@ -413,13 +446,13 @@
 (define_insn "call_value_internal"
   [(set (match_operand                  0 "register_operand" "=r,r")
 	(call (mem:QI (match_operand:SI 1 "rx_call_operand"   "r,Symbol"))
-	      (match_operand:SI         2 "general_operand"   "g,g")))]
+	      (match_operand:SI         2 "general_operand"   "g,g")))
+   (clobber (reg:CC CC_REG))]
   ""
   "@
   jsr\t%1
   bsr\t%A1"
   [(set_attr "length" "2,4")
-   (set_attr "cc" "clobber")
    (set_attr "timings" "33")]
 )
 
@@ -564,11 +597,10 @@
 )
 
 (define_insn "stack_pushm"
-  [(match_parallel                     1 "rx_store_multiple_vector"
+  [(match_parallel 1 "rx_store_multiple_vector"
 		   [(set:SI (reg:SI SP_REG)
 			    (minus:SI (reg:SI SP_REG)
-				      (match_operand:SI
-				       0 "const_int_operand" "n")))])]
+				      (match_operand:SI 0 "const_int_operand" "n")))])]
   "reload_completed"
   {
     rx_emit_stack_pushm (operands);
@@ -591,11 +623,10 @@
 )
 
 (define_insn "stack_popm"
-  [(match_parallel                     1 "rx_load_multiple_vector"
+  [(match_parallel 1 "rx_load_multiple_vector"
 		   [(set:SI (reg:SI SP_REG)
 			    (plus:SI (reg:SI SP_REG)
-				     (match_operand:SI
-				      0 "const_int_operand" "n")))])]
+				     (match_operand:SI 0 "const_int_operand" "n")))])]
   "reload_completed"
   {
     rx_emit_stack_popm (operands, true);
@@ -605,29 +636,29 @@
    (set_attr "timings" "45")] ;; The timing is a guesstimate average timing.
 )
 
+;; FIXME: Add memory destination options ?
 (define_insn "cstoresi4"
-  [(set (match_operand:SI  0 "register_operand" "=r,r,r,r,r,r,r")
-	(match_operator:SI
-	 1 "comparison_operator"
-	 [(match_operand:SI
-	   2 "register_operand"  "r,r,r,r,r,r,r")
-	  (match_operand:SI
-	   3 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")]))]
+  [(set (match_operand:SI   0 "register_operand" "=r,r,r,r,r,r,r")
+	(match_operator:SI  1 "comparison_operator"
+	 [(match_operand:SI 2 "register_operand"  "r,r,r,r,r,r,r")
+	  (match_operand:SI 3 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")]))
+   (clobber (reg:CC CC_REG))] ;; Because the cc flags are set based on comparing ops 2 & 3 not the value in op 0.
   ""
   {
     rx_float_compare_mode = false;
     return "cmp\t%Q3, %Q2\n\tsc%B1.L\t%0";
   }
-  [(set_attr "cc" "clobber") ;; Because cc0 is set based on comparing ops 2 & 3 not the value in op 0.
-   (set_attr "timings" "22,22,22,22,22,22,44")
+  [(set_attr "timings" "22,22,22,22,22,22,44")
    (set_attr "length"  "5,5,6,7,8,9,8")]
 )
 
 (define_expand "movsicc"
-  [(set (match_operand:SI                   0 "register_operand")
-        (if_then_else:SI (match_operand:SI 1 "comparison_operator")
-			 (match_operand:SI  2 "nonmemory_operand")
-			 (match_operand:SI  3 "immediate_operand")))]
+  [(parallel
+    [(set (match_operand:SI                  0 "register_operand")
+	  (if_then_else:SI (match_operand:SI 1 "comparison_operator")
+			   (match_operand:SI 2 "nonmemory_operand")
+			   (match_operand:SI 3 "immediate_operand")))
+     (clobber (reg:CC CC_REG))])] ;; See cstoresi4
   ""
   {
     if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
@@ -638,22 +669,18 @@
 )
 
 (define_insn "*movsieq"
-  [(set (match_operand:SI     0 "register_operand" "=r,r,r")
-	(if_then_else:SI (eq (match_operand:SI
-			      3 "register_operand"  "r,r,r")
-			     (match_operand:SI
-			      4 "rx_source_operand" "riQ,riQ,riQ"))
-			 (match_operand:SI
-			  1 "nonmemory_operand"     "0,i,r")
-			 (match_operand:SI
-			  2 "immediate_operand"     "i,i,i")))]
+  [(set (match_operand:SI                      0 "register_operand" "=r,r,r")
+	(if_then_else:SI (eq (match_operand:SI 3 "register_operand"  "r,r,r")
+			     (match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ"))
+			 (match_operand:SI     1 "nonmemory_operand" "0,i,r")
+			 (match_operand:SI     2 "immediate_operand" "i,i,i")))
+   (clobber (reg:CC CC_REG))] ;; See cstoresi4
   ""
   "@
   cmp\t%Q4, %Q3\n\tstnz\t%2, %0
   cmp\t%Q4, %Q3\n\tmov.l\t%2, %0\n\tstz\t%1, %0
   cmp\t%Q4, %Q3\n\tmov.l\t%1, %0\n\tstnz\t%2, %0"
-  [(set_attr "cc"      "clobber") ;; See cstoresi4
-   (set_attr "length"  "13,19,15")
+  [(set_attr "length"  "13,19,15")
    (set_attr "timings" "22,33,33")]
 )
 
@@ -662,14 +689,14 @@
 	(if_then_else:SI (ne (match_operand:SI 3 "register_operand"  "r,r,r")
 			     (match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ"))
 			 (match_operand:SI     1 "nonmemory_operand" "0,i,r")
-			 (match_operand:SI     2 "immediate_operand" "i,i,i")))]
+			 (match_operand:SI     2 "immediate_operand" "i,i,i")))
+   (clobber (reg:CC CC_REG))] ;; See cstoresi4
   ""
   "@
   cmp\t%Q4, %Q3\n\tstz\t%2, %0
   cmp\t%Q4, %Q3\n\tmov.l\t%2, %0\n\tstnz\t%1, %0
   cmp\t%Q4, %Q3\n\tmov.l\t%1, %0\n\tstz\t%2, %0"
-  [(set_attr "cc"      "clobber") ;; See cstoresi4
-   (set_attr "length"  "13,19,15")
+  [(set_attr "length"  "13,19,15")
    (set_attr "timings" "22,33,33")]
 )
 
@@ -677,24 +704,24 @@
 
 (define_insn "abssi2"
   [(set (match_operand:SI         0 "register_operand" "=r,r")
-        (abs:SI (match_operand:SI 1 "register_operand"  "0,r")))]
+        (abs:SI (match_operand:SI 1 "register_operand"  "0,r")))
+   (set (reg:CC_ZSO CC_REG)
+	(compare:CC_ZSO (abs:SI (match_dup 1))
+			(const_int 0)))]
   ""
   "@
   abs\t%0
   abs\t%1, %0"
-  [(set_attr "cc" "set_zso")
-   (set_attr "length" "2,3")]
+  [(set_attr "length" "2,3")]
 )
 
 (define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand"
-			  "=r,r,r,r,r,r,r,r,r,r,r,r,r")
-	(plus:SI (match_operand:SI
-		  1 "register_operand"
-		  "%0,0,0,0,0,0,0,r,r,r,r,r,0")
-		 (match_operand:SI
-		  2 "rx_source_operand"
-		  "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,r,Sint08,Sint16,Sint24,i,Q")))]
+  [(set (match_operand:SI          0 "register_operand"  "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
+	(plus:SI (match_operand:SI 1 "register_operand"  "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
+		 (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
+   (set (reg:CC_ZSC CC_REG) ;; See subsi3
+	(compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2))
+			(const_int 0)))]
   ""
   "@
   add\t%2, %0
@@ -704,35 +731,38 @@
   add\t%2, %0
   add\t%2, %0
   add\t%2, %0
+  add\t%1, %0
   add\t%2, %1, %0
   add\t%2, %1, %0
   add\t%2, %1, %0
   add\t%2, %1, %0
   add\t%2, %1, %0
   add\t%Q2, %0"
-  [(set_attr "cc" "set_zsc") ;; See subsi3
-   (set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,33")
-   (set_attr "length" "2,2,2,3,4,5,6,3,3,4,5,6,5")]
+  [(set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,11,33")
+   (set_attr "length"   "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
 )
 
 (define_insn "adddi3"
   [(set (match_operand:DI          0 "register_operand" "=r,r,r,r,r,r")
 	(plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0,0")
 		 (match_operand:DI 2 "rx_source_operand"
-				   "r,Sint08,Sint16,Sint24,i,Q")))]
+				   "r,Sint08,Sint16,Sint24,i,Q")))
+   (set (reg:CC_ZSC CC_REG) ;; See subsi3
+	(compare:CC_ZSC (plus:DI (match_dup 1) (match_dup 2))
+			(const_int 0)))]
   ""
   "add\t%L2, %L0\n\tadc\t%H2, %H0"
-  [(set_attr "cc" "set_zsc") ;; See subsi3
-   (set_attr "timings" "22,22,22,22,22,44")
+  [(set_attr "timings" "22,22,22,22,22,44")
    (set_attr "length" "5,7,9,11,13,11")]
 )
 
 (define_insn "andsi3"
   [(set (match_operand:SI         0 "register_operand"  "=r,r,r,r,r,r,r,r,r")
 	(and:SI (match_operand:SI 1 "register_operand"  "%0,0,0,0,0,0,r,r,0")
-		(match_operand:SI
-		 2 "rx_source_operand"
-		 "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))]
+		(match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (and:SI (match_dup 1) (match_dup 2))
+		       (const_int 0)))]
   ""
   "@
   and\t%2, %0
@@ -744,8 +774,7 @@
   and\t%1, %0
   and\t%2, %1, %0
   and\t%Q2, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "timings" "11,11,11,11,11,11,11,33,33")
+  [(set_attr "timings" "11,11,11,11,11,11,11,33,33")
    (set_attr "length" "2,2,3,4,5,6,2,5,5")]
 )
 
@@ -770,12 +799,11 @@
 (define_insn "divsi3"
   [(set (match_operand:SI         0 "register_operand" "=r,r,r,r,r,r")
 	(div:SI (match_operand:SI 1 "register_operand"  "0,0,0,0,0,0")
-		(match_operand:SI
-		 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))]
+		(match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
+   (clobber (reg:CC CC_REG))]
   ""
   "div\t%Q2, %0"
-  [(set_attr "cc" "clobber")
-   (set_attr "timings" "1111") ;; Strictly speaking the timing should be
+  [(set_attr "timings" "1111") ;; Strictly speaking the timing should be
                                ;; 2222, but that is a worst case sceanario.
    (set_attr "length" "3,4,5,6,7,6")]
 )
@@ -783,12 +811,11 @@
 (define_insn "udivsi3"
   [(set (match_operand:SI          0 "register_operand"  "=r,r,r,r,r,r")
 	(udiv:SI (match_operand:SI 1 "register_operand"   "0,0,0,0,0,0")
-		 (match_operand:SI
-		  2 "rx_source_operand"  "r,Sint08,Sint16,Sint24,i,Q")))]
+		 (match_operand:SI 2 "rx_source_operand"  "r,Sint08,Sint16,Sint24,i,Q")))
+   (clobber (reg:CC CC_REG))]
   ""
   "divu\t%Q2, %0"
-  [(set_attr "cc" "clobber")
-   (set_attr "timings" "1010") ;; Strictly speaking the timing should be
+  [(set_attr "timings" "1010") ;; Strictly speaking the timing should be
                                ;; 2020, but that is a worst case sceanario.
    (set_attr "length" "3,4,5,6,7,6")]
 )
@@ -816,12 +843,9 @@
 ;; mulsidi3 pattern.  Immediate mode addressing is not supported
 ;; because gcc cannot handle the expression: (zero_extend (const_int)).
 (define_insn "umulsidi3"
-  [(set (match_operand:DI                          0 "register_operand"
-						   "=r,r")
-        (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand"
-						   "%0,0"))
-                 (zero_extend:DI (match_operand:SI 2 "rx_compare_operand"
-						   "r,Q"))))]
+  [(set (match_operand:DI                          0 "register_operand"	 "=r,r")
+        (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand"  "%0,0"))
+                 (zero_extend:DI (match_operand:SI 2 "rx_compare_operand" "r,Q"))))]
   "! TARGET_BIG_ENDIAN_DATA"
   "emulu\t%Q2, %0"
   [(set_attr "length" "3,6")
@@ -872,33 +896,39 @@
 
 (define_insn "negsi2"
   [(set (match_operand:SI         0 "register_operand" "=r,r")
-        (neg:SI (match_operand:SI 1 "register_operand"  "0,r")))]
+        (neg:SI (match_operand:SI 1 "register_operand"  "0,r")))
+   (set (reg:CC CC_REG)
+	(compare:CC (neg:SI (match_dup 1))
+		    (const_int 0)))]
   ;; The NEG instruction does not comply with -fwrapv semantics.
   ;; See gcc.c-torture/execute/pr22493-1.c for an example of this.
   "! flag_wrapv"
   "@
   neg\t%0
   neg\t%1, %0"
-  [(set_attr "length" "2,3")
-   (set_attr "cc" "set_zsoc")]
+  [(set_attr "length" "2,3")]
 )
 
 (define_insn "one_cmplsi2"
   [(set (match_operand:SI         0 "register_operand" "=r,r")
-	(not:SI (match_operand:SI 1 "register_operand"  "0,r")))]
+	(not:SI (match_operand:SI 1 "register_operand"  "0,r")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (not:SI (match_dup 1))
+		       (const_int 0)))]
   ""
   "@
   not\t%0
   not\t%1, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "length" "2,3")]
+  [(set_attr "length" "2,3")]
 )
 
 (define_insn "iorsi3"
   [(set (match_operand:SI         0 "register_operand" "=r,r,r,r,r,r,r,r,r")
 	(ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
-	        (match_operand:SI 2 "rx_source_operand"
-				  "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))]
+	        (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (ior:SI (match_dup 1) (match_dup 2))
+		       (const_int 0)))]
   ""
   "@
   or\t%2, %0
@@ -910,74 +940,89 @@
   or\t%1, %0
   or\t%2, %1, %0
   or\t%Q2, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "timings" "11,11,11,11,11,11,11,11,33")
+  [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
    (set_attr "length"  "2,2,3,4,5,6,2,3,5")]
 )
 
 (define_insn "rotlsi3"
   [(set (match_operand:SI            0 "register_operand" "=r")
 	(rotate:SI (match_operand:SI 1 "register_operand"  "0")
-		   (match_operand:SI 2 "rx_shift_operand" "rn")))]
+		   (match_operand:SI 2 "rx_shift_operand" "rn")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (rotate:SI (match_dup 1) (match_dup 2))
+		       (const_int 0)))]
   ""
   "rotl\t%2, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "length" "3")]
+  [(set_attr "length" "3")]
 )
 
 (define_insn "rotrsi3"
   [(set (match_operand:SI              0 "register_operand" "=r")
 	(rotatert:SI (match_operand:SI 1 "register_operand"  "0")
-		     (match_operand:SI 2 "rx_shift_operand" "rn")))]
+		     (match_operand:SI 2 "rx_shift_operand" "rn")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (rotatert:SI (match_dup 1) (match_dup 2))
+		       (const_int 0)))]
   ""
   "rotr\t%2, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "length" "3")]
+  [(set_attr "length" "3")]
 )
 
 (define_insn "ashrsi3"
   [(set (match_operand:SI              0 "register_operand" "=r,r,r")
 	(ashiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,r")
-		     (match_operand:SI 2 "rx_shift_operand"  "r,n,n")))]
+		     (match_operand:SI 2 "rx_shift_operand"  "r,n,n")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (ashiftrt:SI (match_dup 1) (match_dup 2))
+		       (const_int 0)))]
   ""
   "@
   shar\t%2, %0
   shar\t%2, %0
   shar\t%2, %1, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "length" "3,2,3")]
+  [(set_attr "length" "3,2,3")]
 )
 
 (define_insn "lshrsi3"
   [(set (match_operand:SI              0 "register_operand" "=r,r,r")
 	(lshiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,r")
-		     (match_operand:SI 2 "rx_shift_operand"  "r,n,n")))]
+		     (match_operand:SI 2 "rx_shift_operand"  "r,n,n")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (lshiftrt:SI (match_dup 1) (match_dup 2))
+		       (const_int 0)))]
   ""
   "@
   shlr\t%2, %0
   shlr\t%2, %0
   shlr\t%2, %1, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "length" "3,2,3")]
+  [(set_attr "length" "3,2,3")]
 )
 
 (define_insn "ashlsi3"
   [(set (match_operand:SI            0 "register_operand" "=r,r,r")
 	(ashift:SI (match_operand:SI 1 "register_operand"  "0,0,r")
-	           (match_operand:SI 2 "rx_shift_operand"  "r,n,n")))]
+	           (match_operand:SI 2 "rx_shift_operand"  "r,n,n")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (ashift:SI (match_dup 1) (match_dup 2))
+		       (const_int 0)))]
   ""
   "@
   shll\t%2, %0
   shll\t%2, %0
   shll\t%2, %1, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "length" "3,2,3")]
+  [(set_attr "length" "3,2,3")]
 )
 
 (define_insn "subsi3"
   [(set (match_operand:SI           0 "register_operand" "=r,r,r,r,r")
 	(minus:SI (match_operand:SI 1 "register_operand"  "0,0,0,r,0")
-		  (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))]
+		  (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))
+   (set (reg:CC_ZSC CC_REG)
+	;; Note - we do not acknowledge that the SUB instruction sets the Overflow
+	;; flag because its interpretation is different from comparing the result
+	;; against zero.  Compile and run gcc.c-torture/execute/cmpsi-1.c to see this.
+	(compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2))
+			(const_int 0)))]
   ""
   "@
   sub\t%2, %0
@@ -985,22 +1030,20 @@
   add\t%N2, %0
   sub\t%2, %1, %0
   sub\t%Q2, %0"
-  [(set_attr "cc" "set_zsc") ;; Note - we do not acknowledge that the SUB
-   ;; instruction sets the Overflow flag because its interpretation is
-   ;; different from comparing the result against zero.  Compile and run
-   ;; gcc.c-torture/execute/cmpsi-1.c to see this.
-   (set_attr "timings" "11,11,11,11,33")
+  [(set_attr "timings" "11,11,11,11,33")
    (set_attr "length" "2,2,6,3,5")]
 )
 
 (define_insn "subdi3"
   [(set (match_operand:DI           0 "register_operand" "=r,r")
 	(minus:DI (match_operand:DI 1 "register_operand"  "0,0")
-		  (match_operand:DI 2 "rx_source_operand" "r,Q")))]
+		  (match_operand:DI 2 "rx_source_operand" "r,Q")))
+   (set (reg:CC_ZSC CC_REG) ;; See subsi3
+	(compare:CC_ZSC (minus:DI (match_dup 1) (match_dup 2))
+			(const_int 0)))]
   ""
   "sub\t%L2, %L0\n\tsbb\t%H2, %H0"
-  [(set_attr "cc" "set_zsc") ;; See subsi3
-   (set_attr "timings" "22,44")
+  [(set_attr "timings" "22,44")
    (set_attr "length" "5,11")]
 )
 
@@ -1008,11 +1051,13 @@
   [(set (match_operand:SI         0 "register_operand" "=r,r,r,r,r,r")
 	(xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
 	        (match_operand:SI 2 "rx_source_operand"
-				  "r,Sint08,Sint16,Sint24,i,Q")))]
+				  "r,Sint08,Sint16,Sint24,i,Q")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (xor:SI (match_dup 1) (match_dup 2))
+		       (const_int 0)))]
   ""
   "xor\t%Q2, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "timings" "11,11,11,11,11,33")
+  [(set_attr "timings" "11,11,11,11,11,33")
    (set_attr "length" "3,4,5,6,7,6")]
 )
 
@@ -1021,64 +1066,76 @@
 (define_insn "addsf3"
   [(set (match_operand:SF          0 "register_operand"  "=r,r,r")
 	(plus:SF (match_operand:SF 1 "register_operand"  "%0,0,0")
-		 (match_operand:SF 2 "rx_source_operand"  "r,F,Q")))]
+		 (match_operand:SF 2 "rx_source_operand"  "r,F,Q")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (plus:SF (match_dup 1) (match_dup 2))
+			(const_int 0)))]
   "ALLOW_RX_FPU_INSNS"
   "fadd\t%2, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "timings" "44,44,66")
+  [(set_attr "timings" "44,44,66")
    (set_attr "length" "3,7,5")]
 )
 
 (define_insn "divsf3"
   [(set (match_operand:SF         0 "register_operand" "=r,r,r")
 	(div:SF (match_operand:SF 1 "register_operand"  "0,0,0")
-		(match_operand:SF 2 "rx_source_operand" "r,F,Q")))]
+		(match_operand:SF 2 "rx_source_operand" "r,F,Q")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (div:SF (match_dup 1) (match_dup 2))
+			(const_int 0)))]
   "ALLOW_RX_FPU_INSNS"
   "fdiv\t%2, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "timings" "1616,1616,1818")
+  [(set_attr "timings" "1616,1616,1818")
    (set_attr "length" "3,7,5")]
 )
 
 (define_insn "mulsf3"
   [(set (match_operand:SF          0 "register_operand" "=r,r,r")
 	(mult:SF (match_operand:SF 1 "register_operand" "%0,0,0")
-		(match_operand:SF  2 "rx_source_operand" "r,F,Q")))]
+		(match_operand:SF  2 "rx_source_operand" "r,F,Q")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (mult:SF (match_dup 1) (match_dup 2))
+			(const_int 0)))]
   "ALLOW_RX_FPU_INSNS"
   "fmul\t%2, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "timings" "33,33,55")
+  [(set_attr "timings" "33,33,55")
    (set_attr "length"  "3,7,5")]
 )
 
 (define_insn "subsf3"
   [(set (match_operand:SF           0 "register_operand" "=r,r,r")
 	(minus:SF (match_operand:SF 1 "register_operand"  "0,0,0")
-		  (match_operand:SF 2 "rx_source_operand" "r,F,Q")))]
+		  (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (minus:SF (match_dup 1) (match_dup 2))
+		       (const_int 0)))]
   "ALLOW_RX_FPU_INSNS"
   "fsub\t%Q2, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "timings" "44,44,66")
+  [(set_attr "timings" "44,44,66")
    (set_attr "length" "3,7,5")]
 )
 
 (define_insn "fix_truncsfsi2"
   [(set (match_operand:SI         0 "register_operand"  "=r,r")
-	(fix:SI (match_operand:SF 1 "rx_compare_operand" "r,Q")))]
+	(fix:SI (match_operand:SF 1 "rx_compare_operand" "r,Q")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (fix:SI (match_dup 1))
+		       (const_int 0)))]
   "ALLOW_RX_FPU_INSNS"
   "ftoi\t%Q1, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "timings" "22,44")
+  [(set_attr "timings" "22,44")
    (set_attr "length" "3,5")]
 )
 
 (define_insn "floatsisf2"
   [(set (match_operand:SF           0 "register_operand"  "=r,r")
-	(float:SF (match_operand:SI 1 "rx_compare_operand" "r,Q")))]
+	(float:SF (match_operand:SI 1 "rx_compare_operand" "r,Q")))
+   (set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS (float:SF (match_dup 1))
+			(const_int 0)))]
   "ALLOW_RX_FPU_INSNS"
   "itof\t%Q1, %0"
-  [(set_attr "cc" "set_zs")
-   (set_attr "timings" "22,44")
+  [(set_attr "timings" "22,44")
    (set_attr "length" "3,6")]
 )
 
@@ -1090,8 +1147,8 @@
 ;; of three instructions at a time.
 
 (define_insn "bitset"
-  [(set:SI (match_operand:SI 0 "register_operand" "=r")
-	   (ior:SI (match_operand:SI 1 "register_operand" "0")
+  [(set:SI (match_operand:SI                    0 "register_operand" "=r")
+	   (ior:SI (match_operand:SI            1 "register_operand" "0")
 		   (ashift:SI (const_int 1)
 			      (match_operand:SI 2 "nonmemory_operand" "ri"))))]
   ""
@@ -1100,8 +1157,8 @@
 )
 
 (define_insn "bitset_in_memory"
-  [(set:QI (match_operand:QI 0 "memory_operand" "=m")
-	   (ior:QI (match_operand:QI 1 "memory_operand" "0")
+  [(set:QI (match_operand:QI                    0 "memory_operand" "=m")
+	   (ior:QI (match_operand:QI            1 "memory_operand" "0")
 		   (ashift:QI (const_int 1)
 			      (match_operand:QI 2 "nonmemory_operand" "ri"))))]
   ""
@@ -1275,14 +1332,10 @@
 )
 
 (define_expand "insv"
-  [(set:SI (zero_extract:SI (match_operand:SI
-			     0 "nonimmediate_operand") ;; Destination
-		            (match_operand
-			     1 "immediate_operand")    ;; # of bits to set
-			    (match_operand
-			     2 "immediate_operand"))   ;; Starting bit
-	   (match_operand
-	    3 "immediate_operand"))]  ;; Bits to insert
+  [(set:SI (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand") ;; Destination
+		            (match_operand    1 "immediate_operand")    ;; # of bits to set
+			    (match_operand    2 "immediate_operand"))   ;; Starting bit
+	   (match_operand	              3 "immediate_operand"))]  ;; Bits to insert
   ""
   {
     if (rx_expand_insv (operands))
@@ -1337,8 +1390,7 @@
    (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVSTR)
    (clobber (reg:SI 1))
    (clobber (reg:SI 2))
-   (clobber (reg:SI 3))
-  ]
+   (clobber (reg:SI 3))]
   ""
   "smovu"
   [(set_attr "length" "2")
@@ -1352,11 +1404,11 @@
    (clobber (reg:SI 1))
    (clobber (reg:SI 2))
    (clobber (reg:SI 3))
-  ]
+   (clobber (reg:CC CC_REG))
+   ]
   ""
   "mov\t%1, r1\n\tmov\t#0, r2\n\tsuntil.b\n\tmov\tr1, %0\n\tsub\t#1, %0"
   [(set_attr "length" "10")
-   (set_attr "cc" "clobber")
    (set_attr "timings" "1111")] ;; The timing is a guesstimate.
 )
 
@@ -1439,17 +1491,12 @@
 )
 
 (define_expand "cmpstrnsi"
-  [(set (match_operand:SI
-	 0 "register_operand") ;; Result
-	(unspec_volatile:SI [(match_operand:BLK
-			      1 "memory_operand") ;; String1
-			     (match_operand:BLK
-			      2 "memory_operand")] ;; String2
+  [(set (match_operand:SI                       0 "register_operand")   ;; Result
+	(unspec_volatile:SI [(match_operand:BLK 1 "memory_operand")     ;; String1
+			     (match_operand:BLK 2 "memory_operand")]    ;; String2
 			    UNSPEC_CMPSTRN))
-   (use (match_operand:SI
-	 3 "register_operand")) ;; Max Length
-   (match_operand:SI
-    4 "immediate_operand")] ;; Known Align
+   (use (match_operand:SI                       3 "register_operand"))  ;; Max Length
+   (match_operand:SI                            4 "immediate_operand")] ;; Known Align
   ""
   {
     rtx str1 = gen_rtx_REG (SImode, 1);
@@ -1466,15 +1513,11 @@
 )
 
 (define_expand "cmpstrsi"
-  [(set (match_operand:SI
-	 0 "register_operand") ;; Result
-	(unspec_volatile:SI [(match_operand:BLK
-			      1 "memory_operand")  ;; String1
-			     (match_operand:BLK
-			      2 "memory_operand")] ;; String2
+  [(set (match_operand:SI                       0 "register_operand")   ;; Result
+	(unspec_volatile:SI [(match_operand:BLK 1 "memory_operand")     ;; String1
+			     (match_operand:BLK 2 "memory_operand")]    ;; String2
 			    UNSPEC_CMPSTRN))
-   (match_operand:SI
-    3 "immediate_operand")] ;; Known Align
+   (match_operand:SI                            3 "immediate_operand")] ;; Known Align
   ""
   {
     rtx str1 = gen_rtx_REG (SImode, 1);
@@ -1498,7 +1541,8 @@
    (use (match_operand:BLK   2 "memory_operand" "m"))
    (clobber (reg:SI 1))
    (clobber (reg:SI 2))
-   (clobber (reg:SI 3))]
+   (clobber (reg:SI 3))
+   (clobber (reg:CC CC_REG))]
   ""
   "scmpu		; Perform the string comparison
    mov     #-1, %0      ; Set up -1 result (which cannot be created
@@ -1639,11 +1683,11 @@
 (define_insn "lrintsf2"
   [(set (match_operand:SI             0 "register_operand"  "=r,r")
 	(unspec:SI [(match_operand:SF 1 "rx_compare_operand" "r,Q")]
-		   UNSPEC_BUILTIN_ROUND))]
+		   UNSPEC_BUILTIN_ROUND))
+   (clobber (reg:CC CC_REG))]
   ""
   "round\t%1, %0"
-  [(set_attr "cc" "clobber")
-   (set_attr "timings" "22,44")   
+  [(set_attr "timings" "22,44")   
    (set_attr "length" "3,5")]
 )
 
@@ -1663,22 +1707,20 @@
 (define_insn "clrpsw"
   [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")]
 	      UNSPEC_BUILTIN_CLRPSW)
-   (clobber (cc0))]
+   (clobber (reg:CC CC_REG))]
   ""
   "clrpsw\t%F0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "clobber")]
+  [(set_attr "length" "2")]
 )
 
 ;; Set Processor Status Word
 (define_insn "setpsw"
   [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")]
 	      UNSPEC_BUILTIN_SETPSW)
-   (clobber (cc0))]
+   (clobber (reg:CC CC_REG))]
   ""
   "setpsw\t%F0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "clobber")]
+  [(set_attr "length" "2")]
 )
 
 ;; Move from control register