diff options
| author | krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-03-24 14:01:54 +0000 |
|---|---|---|
| committer | krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-03-24 14:01:54 +0000 |
| commit | bd97b7d007706034d52dd1f5299c228413bea330 (patch) | |
| tree | 5329e1fc551da9e003eb34ffe96282597a13ca29 /gcc/config/s390/s390.c | |
| parent | bfc4e22d084452c2c5df821593a870766c6bdc7f (diff) | |
| download | gcc-bd97b7d007706034d52dd1f5299c228413bea330.tar.gz | |
S/390: arch12: Add vllezlf instruction.
This adds support for the vector load element and zero instruction and
makes sure it is used when initializing vectors with elements while
setting the rest to 0.
gcc/ChangeLog:
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.c (s390_expand_vec_init): Use vllezl
instruction if possible.
* config/s390/vector.md (vec_halfnumelts): New mode
attribute.
("*vec_vllezlf<mode>"): New pattern.
gcc/testsuite/ChangeLog:
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.target/s390/vxe/vllezlf-1.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246455 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/s390/s390.c')
| -rw-r--r-- | gcc/config/s390/s390.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 416a15ed549..e8003233165 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -6552,6 +6552,34 @@ s390_expand_vec_init (rtx target, rtx vals) return; } + /* Use vector load logical element and zero. */ + if (TARGET_VXE && (mode == V4SImode || mode == V4SFmode)) + { + bool found = true; + + x = XVECEXP (vals, 0, 0); + if (memory_operand (x, inner_mode)) + { + for (i = 1; i < n_elts; ++i) + found = found && XVECEXP (vals, 0, i) == const0_rtx; + + if (found) + { + machine_mode half_mode = (inner_mode == SFmode + ? V2SFmode : V2SImode); + emit_insn (gen_rtx_SET (target, + gen_rtx_VEC_CONCAT (mode, + gen_rtx_VEC_CONCAT (half_mode, + x, + const0_rtx), + gen_rtx_VEC_CONCAT (half_mode, + const0_rtx, + const0_rtx)))); + return; + } + } + } + /* We are about to set the vector elements one by one. Zero out the full register first in order to help the data flow framework to detect it as full VR set. */ |