2013-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

	    Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* config/s390/s390.c (s390_canonicalize_comparison): Don't fold
	int comparisons with an out of range condition code.
	(s390_optimize_nonescaping_tx): Skip empty BBs.
	Generate the new tbegin RTX when removing the FPR clobbers (with
	two SETs).
	(s390_expand_tbegin): Fix the retry loop counter.  Copy CC to the
	result before doing the retry calculations.
	(s390_init_builtins): Make tbegin "returns_twice" and tabort
	"noreturn".
	* config/s390/s390.md (UNSPECV_TBEGIN_TDB): New constant used for
	the TDB setting part of an tbegin.
	("tbegin_1", "tbegin_nofloat_1"): Add a set for the TDB.
	("tx_assist"): Set unused argument to an immediate zero instead of
	loading zero into a GPR and pass it as argument.
	* config/s390/htmxlintrin.h (__TM_simple_begin, __TM_begin):
	Remove inline and related attributes.
	(__TM_nesting_depth, __TM_is_user_abort, __TM_is_named_user_abort)
	(__TM_is_illegal, __TM_is_footprint_exceeded)
	(__TM_is_nested_too_deep, __TM_is_conflict): Fix format value
	check.

2013-11-20  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* gcc.target/s390/htm-1.c: Rename to ...
	* gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c: ... this
	one.
	* gcc.target/s390/htm-xl-intrin-1.c: Rename to ...
	* gcc.target/s390/htm-builtins-compile-3.c: ... this one.
	* gcc.target/s390/htm-builtins-compile-2.c: New testcase.
	* gcc.target/s390/htm-builtins-1.c: New testcase.
	* gcc.target/s390/htm-builtins-2.c: New testcase.
	* gcc.target/s390/s390.exp: Add check for htm machine.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205099 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 16 insertions, 16 deletions

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 8354e263892..d537d29d24f 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -155,6 +155,7 @@
 
    ; Transactional Execution support
    UNSPECV_TBEGIN
+   UNSPECV_TBEGIN_TDB
    UNSPECV_TBEGINC
    UNSPECV_TEND
    UNSPECV_TABORT
@@ -9997,9 +9998,10 @@
 
 (define_insn "tbegin_1"
   [(set (reg:CCRAW CC_REGNUM)
-	(unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand"    "=Q")
-				(match_operand     1 "const_int_operand" " D")]
+	(unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
 			       UNSPECV_TBEGIN))
+   (set (match_operand:BLK 1 "memory_operand" "=Q")
+	(unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
    (clobber (reg:DF 16))
    (clobber (reg:DF 17))
    (clobber (reg:DF 18))
@@ -10018,18 +10020,19 @@
    (clobber (reg:DF 31))]
 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
 ; not supposed to be used for immediates (see genpreds.c).
-  "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"
-  "tbegin\t%0,%x1"
+  "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
+  "tbegin\t%1,%x0"
   [(set_attr "op_type" "SIL")])
 
 ; Same as above but without the FPR clobbers
 (define_insn "tbegin_nofloat_1"
   [(set (reg:CCRAW CC_REGNUM)
-	(unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand"    "=Q")
-				(match_operand     1 "const_int_operand" " D")]
-			       UNSPECV_TBEGIN))]
-  "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"
-  "tbegin\t%0,%x1"
+	(unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
+			       UNSPECV_TBEGIN))
+   (set (match_operand:BLK 1 "memory_operand" "=Q")
+	(unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
+  "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
+  "tbegin\t%1,%x0"
   [(set_attr "op_type" "SIL")])
 
 
@@ -10113,15 +10116,12 @@
 ; Transaction perform processor assist
 
 (define_expand "tx_assist"
-  [(set (match_dup 1) (const_int 0))
-   (unspec_volatile [(match_operand:SI 0 "register_operand" "")
-		     (match_dup 1)
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
+		     (reg:SI GPR0_REGNUM)
 		     (const_int 1)]
 		    UNSPECV_PPA)]
   "TARGET_HTM"
-{
-  operands[1] = gen_reg_rtx (SImode);
-})
+  "")
 
 (define_insn "*ppa"
   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
@@ -10129,5 +10129,5 @@
 		     (match_operand 2 "const_int_operand" "I")]
 		    UNSPECV_PPA)]
   "TARGET_HTM && INTVAL (operands[2]) < 16"
-  "ppa\t%0,%1,1"
+  "ppa\t%0,%1,%2"
   [(set_attr "op_type" "RRF")])