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| author | krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-08-06 10:21:41 +0000 |
|---|---|---|
| committer | krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-08-06 10:21:41 +0000 |
| commit | 044a78dcc96bfa66b3b24cb247a5e0b2327fbebd (patch) | |
| tree | 5e8d1a9d8c249a6b65d1057994534a922a773a6f /gcc/config/s390 | |
| parent | 158dd93660e57427abd865df2c6994f094724cbf (diff) | |
| download | gcc-044a78dcc96bfa66b3b24cb247a5e0b2327fbebd.tar.gz | |
S/390: Clobber VRs in __builtin_tbegin.
gcc/ChangeLog:
* config/s390/s390.c (s390_expand_tbegin): Expand either
tbegin_1_z13 or tbegin_1 depending on VX flag.
* config/s390/s390.md ("tbegin_1_z13"): New expander.
gcc/testsuite/ChangeLog:
* gcc.target/s390/htm-builtins-z13-1.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226672 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/s390')
| -rw-r--r-- | gcc/config/s390/s390.c | 9 | ||||
| -rw-r--r-- | gcc/config/s390/s390.md | 29 |
2 files changed, 37 insertions, 1 deletions
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 7f609baba7b..24a92908556 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -11623,7 +11623,14 @@ s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) } if (clobber_fprs_p) - emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb)); + { + if (TARGET_VX) + emit_insn (gen_tbegin_1_z13 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), + tdb)); + else + emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), + tdb)); + } else emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb)); diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index b23973e4dd0..2be7653d713 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -10626,6 +10626,35 @@ DONE; }) +; Clobber VRs since they don't get restored +(define_insn "tbegin_1_z13" + [(set (reg:CCRAW CC_REGNUM) + (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] + UNSPECV_TBEGIN)) + (set (match_operand:BLK 1 "memory_operand" "=Q") + (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) + (clobber (reg:TI 16)) (clobber (reg:TI 38)) + (clobber (reg:TI 17)) (clobber (reg:TI 39)) + (clobber (reg:TI 18)) (clobber (reg:TI 40)) + (clobber (reg:TI 19)) (clobber (reg:TI 41)) + (clobber (reg:TI 20)) (clobber (reg:TI 42)) + (clobber (reg:TI 21)) (clobber (reg:TI 43)) + (clobber (reg:TI 22)) (clobber (reg:TI 44)) + (clobber (reg:TI 23)) (clobber (reg:TI 45)) + (clobber (reg:TI 24)) (clobber (reg:TI 46)) + (clobber (reg:TI 25)) (clobber (reg:TI 47)) + (clobber (reg:TI 26)) (clobber (reg:TI 48)) + (clobber (reg:TI 27)) (clobber (reg:TI 49)) + (clobber (reg:TI 28)) (clobber (reg:TI 50)) + (clobber (reg:TI 29)) (clobber (reg:TI 51)) + (clobber (reg:TI 30)) (clobber (reg:TI 52)) + (clobber (reg:TI 31)) (clobber (reg:TI 53))] +; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is +; not supposed to be used for immediates (see genpreds.c). + "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" + "tbegin\t%1,%x0" + [(set_attr "op_type" "SIL")]) + (define_insn "tbegin_1" [(set (reg:CCRAW CC_REGNUM) (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |