diff options
| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-12-01 06:24:29 +0000 |
|---|---|---|
| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-12-01 06:24:29 +0000 |
| commit | f24329deac63d825805147fd7c084816af66c318 (patch) | |
| tree | 3c6094673888e95f2c66b8a07e514ddf36be3d53 /gcc/config/sh | |
| parent | 7c57630f83df248e0ed7fb5c8447c0be30852296 (diff) | |
| download | gcc-f24329deac63d825805147fd7c084816af66c318.tar.gz | |
2011-12-01 Basile Starynkevitch <basile@starynkevitch.net>
MELT branch merged with trunk rev 181872 using svnmerge
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@181873 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/sh')
| -rw-r--r-- | gcc/config/sh/constraints.md | 3 | ||||
| -rw-r--r-- | gcc/config/sh/sh.c | 8 | ||||
| -rw-r--r-- | gcc/config/sh/sh.h | 6 |
3 files changed, 16 insertions, 1 deletions
diff --git a/gcc/config/sh/constraints.md b/gcc/config/sh/constraints.md index 40d0d0b4b99..59e7de66662 100644 --- a/gcc/config/sh/constraints.md +++ b/gcc/config/sh/constraints.md @@ -75,6 +75,9 @@ (define_register_constraint "t" "T_REGS" "T register.") +(define_register_constraint "u" "NON_SP_REGS" + "Non-stack-pointer register.") + (define_register_constraint "w" "FP0_REGS" "Floating-point register 0.") diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 2545a63e724..870c39f2602 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -12432,6 +12432,14 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, if (rclass != GENERAL_REGS && REG_P (x) && TARGET_REGISTER_P (REGNO (x))) return GENERAL_REGS; + + /* If here fall back to loading FPUL register through general registers. + This case can happen when movsi_ie insn is picked initially to + load/store the FPUL register from/to another register, and then the + other register is allocated on the stack. */ + if (rclass == FPUL_REGS && true_regnum (x) == -1) + return GENERAL_REGS; + return NO_REGS; } diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 1b98745866e..8ab1f10e31e 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -1059,6 +1059,7 @@ enum reg_class MAC_REGS, FPUL_REGS, SIBCALL_REGS, + NON_SP_REGS, GENERAL_REGS, FP0_REGS, FP_REGS, @@ -1084,6 +1085,7 @@ enum reg_class "MAC_REGS", \ "FPUL_REGS", \ "SIBCALL_REGS", \ + "NON_SP_REGS", \ "GENERAL_REGS", \ "FP0_REGS", \ "FP_REGS", \ @@ -1116,6 +1118,8 @@ enum reg_class { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \ /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ +/* NON_SP_REGS: */ \ + { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ /* GENERAL_REGS: */ \ { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ /* FP0_REGS: */ \ @@ -2072,7 +2076,7 @@ struct sh_args { register information here is not used for SFmode. */ #define REGCLASS_HAS_GENERAL_REG(CLASS) \ - ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \ + ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \ || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) #define REGCLASS_HAS_FP_REG(CLASS) \ |