Sun Niagara specific optimizations.

	* config.gcc: Recognize niagara as target.
	* config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Mention Niagara.
	(TARGET_CPU_niagara): Define.
	(CPP_CPU64_DEFAULT_SPEC): Define __sparc_v9__ for Niagara.
	(ASM_CPU64_DEFAULT_SPEC): Pass -Av9b for Niagara.
	(CPP_CPU_SPEC): Handle -mcpu=niagara.
	(ASM_CPU_SPEC): Likewise.
	(PROCESSOR_NIAGARA): New enum entry.
	(REGISTER_MOVE_COST): Handle Niagara.
	(BRANCH_COST, PREFETCH_BLOCK, SIMULTANEOUS_PREFETCHES): Likewise.
	* config/sparc/sparc.c (niagara_costs): New processor_costs entry.
	(sparc_override_options): Recognize "niagara", set appropriate
	default MASK_* values for it, and align functions to 32-bytes
	by default just like ULTRASPARC/ULTRASPARC3.
	(sparc_initialize_trampoline): Handle niagara like ultrasparc.
	(sparc64_initialize_trampoline): Likewise.
	(sparc_use_sched_lookahead): Use zero for niagara.
	(sparc_issue_rate): Use one for niagara.
	* config/sparc/niagara.md: New file.
	* config/sparc/sparc.md: Include it.
	* config/sparc/sol2-bi.h (CPP_CPU64_DEFAULT_SPEC,
	ASM_CPU32_DEFAULT_SPEC, ASM_CPU64_DEFAULT_SPEC): Set appropriately
	when default cpu is niagara.
	(CPP_CPU_SPEC): Handle -mcpu=niagara.
	(ASM_CPU_SPEC): Likewise.
	* config/sparc/sol2.h (ASM_CPU_DEFAULT_SPEC): Set appropriately
	when default cpu is niagara.
	(ASM_CPU_SPEC): Handle -mcpu=niagara.
	* config/sparc/linux64.h: Handle a default of TARGET_CPU_niagara
	just like v9/ultrasparc/ultrasparc3.
	* doc/invoke.texi: Add documentation for "niagara" and improve
	existing documentation for ultrasparc variants.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@111648 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 119 insertions, 0 deletions

diff --git a/gcc/config/sparc/niagara.md b/gcc/config/sparc/niagara.md
new file mode 100644
index 00000000000..ea431b521d6
--- /dev/null
+++ b/gcc/config/sparc/niagara.md
@@ -0,0 +1,119 @@
+;; Scheduling description for Niagara.
+;;   Copyright (C) 2006 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA.
+
+;; Niagara is a single-issue processor.
+
+(define_automaton "niagara_0")
+
+(define_cpu_unit "niag_pipe" "niagara_0")
+
+(define_insn_reservation "niag_5cycle" 5
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "multi,flushw,iflush,trap"))
+  "niag_pipe*5")
+
+(define_insn_reservation "niag_4cycle" 4
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "savew"))
+  "niag_pipe*4")
+
+/* Most basic operations are single-cycle. */
+(define_insn_reservation "niag_ialu" 1
+ (and (eq_attr "cpu" "niagara")
+   (eq_attr "type" "ialu,shift,compare,cmove"))
+ "niag_pipe")
+
+(define_insn_reservation "niag_imul" 11
+ (and (eq_attr "cpu" "niagara")
+   (eq_attr "type" "imul"))
+ "niag_pipe*11")
+
+(define_insn_reservation "niag_idiv" 72
+ (and (eq_attr "cpu" "niagara")
+   (eq_attr "type" "idiv"))
+ "niag_pipe*72")
+
+(define_insn_reservation "niag_branch" 3
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch"))
+  "niag_pipe*3")
+
+(define_insn_reservation "niag_3cycle_load" 3
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "load"))
+  "niag_pipe*3")
+
+(define_insn_reservation "niag_9cycle_load" 9
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpload"))
+  "niag_pipe*9")
+
+(define_insn_reservation "niag_1cycle_store" 1
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "store"))
+  "niag_pipe")
+
+(define_insn_reservation "niag_8cycle_store" 8
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpstore"))
+  "niag_pipe*8")
+
+/* Things incorrectly modelled here:
+ *  FPADD{s,d}: 26 cycles
+ *  FPSUB{s,d}: 26 cycles
+ *  FABSD: 26 cycles
+ *  F{s,d}TO{s,d}: 26 cycles
+ *  F{s,d}TO{i,x}: 26 cycles
+ *  FSMULD: 29 cycles
+ */
+(define_insn_reservation "niag_fmov" 8
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpmove,fpcmove,fpcrmove"))
+  "niag_pipe*8")
+
+(define_insn_reservation "niag_fpcmp" 26
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpcmp"))
+  "niag_pipe*26")
+
+(define_insn_reservation "niag_fmult" 29
+ (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpmul"))
+  "niag_pipe*29")
+
+(define_insn_reservation "niag_fdivs" 54
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpdivs"))
+  "niag_pipe*54")
+
+(define_insn_reservation "niag_fdivd" 83
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpdivd"))
+  "niag_pipe*83")
+
+/* Things incorrectly modelled here:
+ *  FPADD{16,32}: 10 cycles
+ *  FPSUB{16,32}: 10 cycles
+ *  FALIGNDATA: 10 cycles
+ */
+(define_insn_reservation "niag_vis" 8
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist"))
+  "niag_pipe*8")