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author | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2001-12-16 02:26:58 +0000 |
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committer | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2001-12-16 02:26:58 +0000 |
commit | 55d52cfef924f6373a649dae4a19d3d5b42b5a62 (patch) | |
tree | 9f411006b9b7f87081fc8ba542ba8b87b2604ce4 /gcc/config/sparc/sparc.c | |
parent | 8b4a4127efde4bd45ebefe807e0ec8c36993e3b6 (diff) | |
download | gcc-55d52cfef924f6373a649dae4a19d3d5b42b5a62.tar.gz |
* config/sparc/sparc.c (mems_ok_for_ldd_peep): Rename from
addrs_ok_for_ldd_peep_withmem; take MEMs as parameters, not
addrs; eliminate restriction of only using fp and sp as base
registers.
* config/sparc/sparc-protos.h: Update.
* config/sparc/sparc.md (movdi): Use TARGET_V9 not TARGET_ARCH64.
(*cmp_cc_set, *cmp_ccx_set64, *movdi_zero): New insns derived
from old define_peepholes.
Convert all the ldd/std peepholes to peephole2.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@48059 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/sparc/sparc.c')
-rw-r--r-- | gcc/config/sparc/sparc.c | 36 |
1 files changed, 16 insertions, 20 deletions
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 2807add2849..48906d46bf4 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -5646,27 +5646,28 @@ registers_ok_for_ldd_peep (reg1, reg2) return (REGNO (reg1) == REGNO (reg2) - 1); } -/* Return 1 if addr1 and addr2 are suitable for use in an ldd or - std insn. - - This can only happen when addr1 and addr2 are consecutive memory - locations (addr1 + 4 == addr2). addr1 must also be aligned on a - 64 bit boundary (addr1 % 8 == 0). - - We know %sp and %fp are kept aligned on a 64 bit boundary. Other - registers are assumed to *never* be properly aligned and are - rejected. - - Knowing %sp and %fp are kept aligned on a 64 bit boundary, we - need only check that the offset for addr1 % 8 == 0. */ +/* Return 1 if the addresses in mem1 and mem2 are suitable for use in + an ldd or std insn. + + This can only happen when addr1 and addr2, the addresses in mem1 + and mem2, are consecutive memory locations (addr1 + 4 == addr2). + addr1 must also be aligned on a 64-bit boundary. */ int -addrs_ok_for_ldd_peep (addr1, addr2) - rtx addr1, addr2; +mems_ok_for_ldd_peep (mem1, mem2) + rtx mem1, mem2; { + rtx addr1, addr2; unsigned int reg1; int offset1; + addr1 = XEXP (mem1, 0); + addr2 = XEXP (mem2, 0); + + /* mem1 should be aligned on a 64-bit boundary */ + if (MEM_ALIGN (mem1) < 64) + return 0; + /* Extract a register number and offset (if used) from the first addr. */ if (GET_CODE (addr1) == PLUS) { @@ -5699,11 +5700,6 @@ addrs_ok_for_ldd_peep (addr1, addr2) || GET_CODE (XEXP (addr2, 1)) != CONST_INT) return 0; - /* Only %fp and %sp are allowed. Additionally both addresses must - use the same register. */ - if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM) - return 0; - if (reg1 != REGNO (XEXP (addr2, 0))) return 0; |