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authordavem <davem@138bc75d-0d04-0410-961f-82ee72b054a4>2002-05-04 05:03:45 +0000
committerdavem <davem@138bc75d-0d04-0410-961f-82ee72b054a4>2002-05-04 05:03:45 +0000
commitaa5841a80f6d177672330041a580ad98f604f251 (patch)
treeed7f60249865c4f7da0bed4baafd88f7f586650a /gcc/config/sparc/sparclet.md
parent71731aa449b2cf1d2f5737f30e9c12b743be5a9f (diff)
downloadgcc-aa5841a80f6d177672330041a580ad98f604f251.tar.gz
2002-05-03 David S. Miller <davem@redhat.com>
* config/sparc/sparc.md (DFA schedulers): Split out... * config/sparc/cypress.md, config/sparc/hypersparc.md, config/sparc/sparclet.md, config/sparc/supersparc.md, config/sparc/ultra1_2.md, config/sparc/ultra3.md: ... into here. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@53146 138bc75d-0d04-0410-961f-82ee72b054a4
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+;; Scheduling description for Sparclet.
+;; Copyright (C) 2002 Free Software Foundation, Inc.
+;;
+;; This file is part of GNU CC.
+;;
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; The Sparclet is a single-issue processor.
+
+(define_automaton "sparclet")
+
+(define_cpu_unit "sl_load0,sl_load1,sl_load2,sl_load3" "sparclet")
+(define_cpu_unit "sl_store,sl_imul" "sparclet")
+
+(define_reservation "sl_load_any" "(sl_load0 | sl_load1 | sl_load2 | sl_load3)")
+(define_reservation "sl_load_all" "(sl_load0 + sl_load1 + sl_load2 + sl_load3)")
+
+(define_insn_reservation "sl_ld" 3
+ (and (eq_attr "cpu" "tsc701")
+ (eq_attr "type" "load,sload"))
+ "sl_load_any, sl_load_any, sl_load_any")
+
+(define_insn_reservation "sl_st" 3
+ (and (eq_attr "cpu" "tsc701")
+ (eq_attr "type" "store"))
+ "(sl_store+sl_load_all)*3")
+
+(define_insn_reservation "sl_imul" 5
+ (and (eq_attr "cpu" "tsc701")
+ (eq_attr "type" "imul"))
+ "sl_imul*5")