optc-gen.awk: Handle stand-alone Mask records.

	* optc-gen.awk: Handle stand-alone Mask records.
	* opth-gen.awk: Likewise.
	* doc/options.texi (Option file format): Document them.
	* config.gcc (sparc-*-netbsdelf*, sparc-*-linux*, sparc64-*-freebsd*,
	sparc64-*-linux*, sparc64-*-netbsd*): Add long-double-switch.opt.
	(sparc64-*-openbsd*, sparc64-*-elf*): Add little-endian.opt.
	* config/sparc/sparc.h (MASK_FPU, MASK_UNALIGNED_DOUBLES,
	MASK_V8, MASK_SPARCLITE, MASK_SPARCLET, MASK_V9,
	MASK_DEPRECATED_V8_INSNS, MASK_IMPURE_TEXT, MASK_APP_REGS,
	MASK_HARD_QUAD, MASK_LITTLE_ENDIAN, MASK_PTR64, MASK_64BIT,
	MASK_STACK_BIAS, MASK_FPU_SET, MASK_VIS, MASK_V8PLUS,
	MASK_FASTER_STRUCTS, MASK_LONG_DOUBLE_128): Delete.
	(TARGET_FPU, TARGET_UNALIGNED_DOUBLES, TARGET_V8, TARGET_SPARCLITE,
	TARGET_SPARCLET, TARGET_V9, TARGET_DEPRECATED_V8_INSNS,
	TARGET_IMPURE_TEXT, TARGET_APP_REGS, MASK_HARD_QUAD,
	TARGET_LITTLE_ENDIAN, TARGET_PTR64, TARGET_64BIT, MASK_STACK_BIAS,
	TARGET_FPU_SET, TARGET_VIS, TARGET_V8PLUS, TARGET_FASTER_STRUCTS,
	TARGET_LONG_DOUBLE_128): Likewise.
	(TARGET_SWITCHES, SUBTARGET_SWITCHES): Likewise.
	(TARGET_OPTIONS, SUBTARGET_OPTIONS): Likewise.
	* config/sparc/freebsd.h (SUBTARGET_SWITCHES): Likewise.
	* config/sparc/linux.h (SUBTARGET_SWITCHES): Likewise.
	* config/sparc/linux64.h (SUBTARGET_SWITCHES): Likewise.
	* config/sparc/netbsd-elf.h (SUBTARGET_SWITCHES): Likewise.
	* config/sparc/sp64-elf.h (SUBTARGET_SWITCHES): Likewise.
	* config/sparc/sparc.c (fpu_option_set): New global.
	(sparc_handle_option): New function.
	(sparc_override_options): Test fpu_option_set.
	(TARGET_DEFAULT_TARGET_FLAGS): Set to TARGET_DEFAULT.
	(TARGET_HANDLE_OPTION): Set to sparc_handle_option.
	* config/sparc/sparc.opt: New file.
	* config/sparc/little-endian.opt: Likewise.
	* config/sparc/long-double-switch.opt: Likewise.

From-SVN: r98078

10 files changed, 225 insertions, 229 deletions

diff --git a/gcc/config/sparc/freebsd.h b/gcc/config/sparc/freebsd.h
index c032d644be0..aefa1d45ab8 100644
--- a/gcc/config/sparc/freebsd.h
+++ b/gcc/config/sparc/freebsd.h
@@ -72,11 +72,6 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
 
 /* Definitions for 64-bit SPARC running systems with ELF. */
 
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES						    \
-  {"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") },  \
-  {"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
-
 #undef  TARGET_VERSION
 #define TARGET_VERSION fprintf (stderr, " (FreeBSD/sparc64 ELF)");
 
diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h
index feec79c06b7..fdad997056b 100644
--- a/gcc/config/sparc/linux.h
+++ b/gcc/config/sparc/linux.h
@@ -86,11 +86,6 @@ Boston, MA 02111-1307, USA.  */
 #undef TARGET_VERSION
 #define TARGET_VERSION fprintf (stderr, " (sparc GNU/Linux with ELF)");
 
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
-{"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
-
 #undef SIZE_TYPE
 #define SIZE_TYPE "unsigned int"
  
diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h
index ac3a21ac877..3a4613b89c9 100644
--- a/gcc/config/sparc/linux64.h
+++ b/gcc/config/sparc/linux64.h
@@ -106,11 +106,6 @@ Boston, MA 02111-1307, USA.  */
 #undef SPARC_DEFAULT_CMODEL
 #define SPARC_DEFAULT_CMODEL CM_MEDLOW
 
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES						    \
-{"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") },  \
-{"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
-
 #undef WCHAR_TYPE
 #define WCHAR_TYPE "int"
 
diff --git a/gcc/config/sparc/little-endian.opt b/gcc/config/sparc/little-endian.opt
new file mode 100644
index 00000000000..81a87585223
--- /dev/null
+++ b/gcc/config/sparc/little-endian.opt
@@ -0,0 +1,28 @@
+; Options for the SPARC port of the compiler
+;
+; Copyright (C) 2005 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 2, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT
+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+; License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING.  If not, write to the Free
+; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+; 02111-1307, USA.
+
+mlittle-endian
+Target Report RejectNegative Mask(LITTLE_ENDIAN) MaskExists
+Generate code for little-endian
+
+mbig-endian
+Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
+Generate code for big-endian
diff --git a/gcc/config/sparc/long-double-switch.opt b/gcc/config/sparc/long-double-switch.opt
new file mode 100644
index 00000000000..565cb8e09b2
--- /dev/null
+++ b/gcc/config/sparc/long-double-switch.opt
@@ -0,0 +1,28 @@
+; Options for the SPARC port of the compiler
+;
+; Copyright (C) 2005 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 2, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT
+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+; License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING.  If not, write to the Free
+; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+; 02111-1307, USA.
+
+mlong-double-128
+Target Report RejectNegative Mask(LONG_DOUBLE_128) MaskExists
+Use 128-bit long double
+
+mlong-double-64
+Target Report RejectNegative InverseMask(LONG_DOUBLE_128)
+Use 64-bit long double
diff --git a/gcc/config/sparc/netbsd-elf.h b/gcc/config/sparc/netbsd-elf.h
index c86adc5fe01..f12a00a42e9 100644
--- a/gcc/config/sparc/netbsd-elf.h
+++ b/gcc/config/sparc/netbsd-elf.h
@@ -195,13 +195,6 @@ Boston, MA 02111-1307, USA.  */
   { "netbsd_entry_point",	NETBSD_ENTRY_POINT },
 
 
-/* What extra switches do we need?  */
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-  {"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
-  {"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
-
-
 /* Build a compiler that supports -m32 and -m64?  */
 
 #ifdef SPARC_BI_ARCH
diff --git a/gcc/config/sparc/sp64-elf.h b/gcc/config/sparc/sp64-elf.h
index e75a5f53bf6..dcb79ee95fa 100644
--- a/gcc/config/sparc/sp64-elf.h
+++ b/gcc/config/sparc/sp64-elf.h
@@ -81,12 +81,6 @@ crtbegin.o%s \
    || (CHAR) == 'h' \
    || (CHAR) == 'z')
 
-/* V9 chips can handle either endianness.  */
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"big-endian", -MASK_LITTLE_ENDIAN, N_("Generate code for big endian") }, \
-{"little-endian", MASK_LITTLE_ENDIAN, N_("Generate code for little endian") },
-
 #undef BYTES_BIG_ENDIAN
 #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
 
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index bae1b83ee21..a429bcfb8a5 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -299,6 +299,7 @@ static HOST_WIDE_INT frame_base_offset;
 /* 1 if the next opcode is to be specially indented.  */
 int sparc_indent_opcode = 0;
 
+static bool sparc_handle_option (size_t, const char *, int);
 static void sparc_init_modes (void);
 static void scan_record_type (tree, int *, int *, int *);
 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
@@ -372,6 +373,7 @@ const struct attribute_spec sparc_attribute_table[];
 
 /* Code model option as passed by user.  */
 const char *sparc_cmodel_string;
+
 /* Parsed value.  */
 enum cmodel sparc_cmodel;
 
@@ -388,7 +390,10 @@ struct sparc_cpu_select sparc_select[] =
 
 /* CPU type.  This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx.  */
 enum processor_type sparc_cpu;
-
+
+/* Whetheran FPU option was specified.  */
+static bool fpu_option_set = false;
+
 /* Initialize the GCC target structure.  */
 
 /* The sparc default is to use .half rather than .short for aligned
@@ -506,11 +511,45 @@ enum processor_type sparc_cpu;
 #undef TARGET_RELAXED_ORDERING
 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
 
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION sparc_handle_option
+
 #undef TARGET_ASM_FILE_END
 #define TARGET_ASM_FILE_END sparc_file_end
 
 struct gcc_target targetm = TARGET_INITIALIZER;
-
+
+/* Implement TARGET_HANDLE_OPTION.  */
+
+static bool
+sparc_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
+{
+  switch (code)
+    {
+    case OPT_mfpu:
+    case OPT_mhard_float:
+    case OPT_msoft_float:
+      fpu_option_set = true;
+      break;
+
+    case OPT_mcpu_:
+      sparc_select[1].string = arg;
+      break;
+
+    case OPT_mtune_:
+      sparc_select[2].string = arg;
+      break;
+
+    case OPT_mcmodel_:
+      sparc_cmodel_string = arg;
+      break;
+    }
+
+  return true;
+}
+
 /* Validate and override various options, and do some machine dependent
    initialization.  */
 
@@ -657,13 +696,9 @@ sparc_override_options (void)
     }
 
   /* If -mfpu or -mno-fpu was explicitly used, don't override with
-     the processor default.  Clear MASK_FPU_SET to avoid confusing
-     the reverse mapping from switch values to names.  */
-  if (TARGET_FPU_SET)
-    {
-      target_flags = (target_flags & ~MASK_FPU) | fpu;
-      target_flags &= ~MASK_FPU_SET;
-    }
+     the processor default.  */
+  if (fpu_option_set)
+    target_flags = (target_flags & ~MASK_FPU) | fpu;
 
   /* Don't allow -mvis if FPU is disabled.  */
   if (! TARGET_FPU)
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index ae8624d076f..f00852a7a1f 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -483,122 +483,14 @@ extern enum cmodel sparc_cmodel;
 /* Show we can debug even without a frame pointer.  */
 #define CAN_DEBUG_WITHOUT_FP
 
+/* Option handling.  */
+
 #define OVERRIDE_OPTIONS  sparc_override_options ()
 
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Nonzero if we should generate code to use the fpu.  */
-#define MASK_FPU 1
-#define TARGET_FPU (target_flags & MASK_FPU)
-
-/* Nonzero if we should assume that double pointers might be unaligned.
-   This can happen when linking gcc compiled code with other compilers,
-   because the ABI only guarantees 4 byte alignment.  */
-#define MASK_UNALIGNED_DOUBLES 4
-#define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
-
-/* Nonzero means that we should generate code for a v8 sparc.  */
-#define MASK_V8 0x8
-#define TARGET_V8 (target_flags & MASK_V8)
-
-/* Nonzero means that we should generate code for a sparclite.
-   This enables the sparclite specific instructions, but does not affect
-   whether FPU instructions are emitted.  */
-#define MASK_SPARCLITE 0x10
-#define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
-
-/* Nonzero if we're compiling for the sparclet.  */
-#define MASK_SPARCLET 0x20
-#define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
-
-/* Nonzero if we're compiling for v9 sparc.
-   Note that v9's can run in 32 bit mode so this doesn't necessarily mean
-   the word size is 64.  */
-#define MASK_V9 0x40
-#define TARGET_V9 (target_flags & MASK_V9)
-
-/* Nonzero to generate code that uses the instructions deprecated in
-   the v9 architecture.  This option only applies to v9 systems.  */
-/* ??? This isn't user selectable yet.  It's used to enable such insns
-   on 32 bit v9 systems and for the moment they're permanently disabled
-   on 64 bit v9 systems.  */
-#define MASK_DEPRECATED_V8_INSNS 0x80
-#define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
-
 /* Mask of all CPU selection flags.  */
 #define MASK_ISA \
 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
 
-/* Nonzero means don't pass `-assert pure-text' to the linker.  */
-#define MASK_IMPURE_TEXT 0x100
-#define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
-
-/* 0x200 is unused */
-
-/* Nonzero means use the registers that the SPARC ABI reserves for
-   application software.  This must be the default to coincide with the
-   setting in FIXED_REGISTERS.  */
-#define MASK_APP_REGS 0x400
-#define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
-
-/* Option to select how quad word floating point is implemented.
-   When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
-   Otherwise, we use the SPARC ABI quad library functions.  */
-#define MASK_HARD_QUAD 0x800
-#define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
-
-/* Nonzero on little-endian machines.  */
-/* ??? Little endian support currently only exists for sparc86x-elf and
-   sparc64-elf configurations.  May eventually want to expand the support
-   to all targets, but for now it's kept local to only those two.  */
-#define MASK_LITTLE_ENDIAN 0x1000
-#define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
-
-/* 0x2000, 0x4000 are unused */
-
-/* Nonzero if pointers are 64 bits.  */
-#define MASK_PTR64 0x8000
-#define TARGET_PTR64 (target_flags & MASK_PTR64)
-
-/* Nonzero if generating code to run in a 64 bit environment.
-   This is intended to only be used by TARGET_ARCH{32,64} as they are the
-   mechanism used to control compile time or run time selection.  */
-#define MASK_64BIT 0x10000
-#define TARGET_64BIT (target_flags & MASK_64BIT)
-
-/* 0x20000,0x40000 unused */
-
-/* Nonzero means use a stack bias of 2047.  Stack offsets are obtained by
-   adding 2047 to %sp.  This option is for v9 only and is the default.  */
-#define MASK_STACK_BIAS 0x80000
-#define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
-
-/* 0x100000,0x200000 unused */
-
-/* Nonzero means -m{,no-}fpu was passed on the command line.  */
-#define MASK_FPU_SET 0x400000
-#define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
-
-/* Use the UltraSPARC Visual Instruction Set extensions.  */
-#define MASK_VIS 0x1000000
-#define TARGET_VIS (target_flags & MASK_VIS)
-
-/* Compile for Solaris V8+.  32 bit Solaris preserves the high bits of
-   the current out and global registers and Linux 2.2+ as well.  */
-#define MASK_V8PLUS 0x2000000
-#define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
-
-/* Force a the fastest alignment on structures to take advantage of
-   faster copies.  */
-#define MASK_FASTER_STRUCTS 0x4000000
-#define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
-
-/* Use IEEE quad long double.  */
-#define MASK_LONG_DOUBLE_128 0x8000000
-#define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
-
 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
    TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
    to get high 32 bits.  False in V8+ or V9 because multiply stores
@@ -613,79 +505,11 @@ extern int target_flags;
   (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET	\
    || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
 
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  { {"fpu", MASK_FPU | MASK_FPU_SET,					\
-     N_("Use hardware fp") },						\
-    {"no-fpu", -MASK_FPU,						\
-     N_("Do not use hardware fp") },					\
-    {"no-fpu", MASK_FPU_SET,				NULL, },	\
-    {"hard-float", MASK_FPU | MASK_FPU_SET,				\
-     N_("Use hardware fp") },						\
-    {"soft-float", -MASK_FPU,						\
-     N_("Do not use hardware fp") },					\
-    {"soft-float", MASK_FPU_SET,			NULL },		\
-    {"unaligned-doubles", MASK_UNALIGNED_DOUBLES,			\
-     N_("Assume possible double misalignment") },			\
-    {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES,			\
-     N_("Assume all doubles are aligned") },				\
-    {"impure-text", MASK_IMPURE_TEXT,					\
-     N_("Pass -assert pure-text to linker") }, 				\
-    {"no-impure-text", -MASK_IMPURE_TEXT,				\
-     N_("Do not pass -assert pure-text to linker") }, 			\
-    {"app-regs", MASK_APP_REGS,						\
-     N_("Use ABI reserved registers") },				\
-    {"no-app-regs", -MASK_APP_REGS,					\
-     N_("Do not use ABI reserved registers") }, 			\
-    {"hard-quad-float", MASK_HARD_QUAD,					\
-     N_("Use hardware quad fp instructions") }, 			\
-    {"soft-quad-float", -MASK_HARD_QUAD,				\
-     N_("Do not use hardware quad fp instructions") }, 			\
-    {"v8plus", MASK_V8PLUS,						\
-     N_("Compile for v8plus ABI") },					\
-    {"no-v8plus", -MASK_V8PLUS,						\
-     N_("Do not compile for v8plus ABI") }, 				\
-    {"vis", MASK_VIS,							\
-     N_("Utilize Visual Instruction Set") }, 				\
-    {"no-vis", -MASK_VIS,						\
-     N_("Do not utilize Visual Instruction Set") }, 			\
-    {"ptr64", MASK_PTR64,						\
-     N_("Pointers are 64-bit") }, 					\
-    {"ptr32", -MASK_PTR64,						\
-     N_("Pointers are 32-bit") }, 					\
-    {"32", -MASK_64BIT,							\
-     N_("Use 32-bit ABI") }, 						\
-    {"64", MASK_64BIT,							\
-     N_("Use 64-bit ABI") }, 						\
-    {"stack-bias", MASK_STACK_BIAS,					\
-     N_("Use stack bias") }, 						\
-    {"no-stack-bias", -MASK_STACK_BIAS,					\
-     N_("Do not use stack bias") }, 					\
-    {"faster-structs", MASK_FASTER_STRUCTS,				\
-     N_("Use structs on stronger alignment for double-word copies") }, 	\
-    {"no-faster-structs", -MASK_FASTER_STRUCTS,				\
-     N_("Do not use structs on stronger alignment for double-word copies") }, \
-    {"relax", 0,							\
-     N_("Optimize tail call instructions in assembler and linker") },	\
-    {"no-relax", 0,							\
-     N_("Do not optimize tail call instructions in assembler or linker") }, \
-    SUBTARGET_SWITCHES			\
-    { "", TARGET_DEFAULT, ""}}
-
 /* MASK_APP_REGS must always be the default because that's what
    FIXED_REGISTERS is set to and -ffixed- is processed before
    CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs).  */
 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
 
-/* This is meant to be redefined in target specific files.  */
-#define SUBTARGET_SWITCHES
-
 /* Processor type.
    These must match the values for the cpu attribute in sparc.md.  */
 enum processor_type {
@@ -712,20 +536,6 @@ extern enum processor_type sparc_cpu;
    Every file includes us, but not every file includes insn-attr.h.  */
 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
 
-#define TARGET_OPTIONS \
-{								\
-  { "cpu=",  &sparc_select[1].string,				\
-    N_("Use features of and schedule code for given CPU"), 0},	\
-  { "tune=", &sparc_select[2].string,				\
-    N_("Schedule code for given CPU"), 0},			\
-  { "cmodel=", &sparc_cmodel_string,				\
-    N_("Use given SPARC code model"), 0},			\
-  SUBTARGET_OPTIONS 						\
-}
-
-/* This is meant to be redefined in target specific files.  */
-#define SUBTARGET_OPTIONS
-
 /* Support for a compile-time default CPU, et cetera.  The rules are:
    --with-cpu is ignored if -mcpu is specified.
    --with-tune is ignored if -mtune is specified.
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
new file mode 100644
index 00000000000..88a603c6f56
--- /dev/null
+++ b/gcc/config/sparc/sparc.opt
@@ -0,0 +1,123 @@
+; Options for the SPARC port of the compiler
+;
+; Copyright (C) 2005 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 2, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT
+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+; License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING.  If not, write to the Free
+; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+; 02111-1307, USA.
+
+mfpu
+Target Report Mask(FPU)
+Use hardware FP
+
+mhard-float
+Target RejectNegative Mask(FPU) MaskExists
+Use hardware FP
+
+msoft-float
+Target RejectNegative InverseMask(FPU)
+Do not use hardware FP
+
+munaligned-doubles
+Target Report Mask(UNALIGNED_DOUBLES)
+Assume possible double misalignment
+
+mimpure-text
+Target Report
+Pass -assert pure-text to linker
+
+mapp-regs
+Target Report Mask(APP_REGS)
+Use ABI reserved registers
+
+mhard-quad-float
+Target Report RejectNegative Mask(HARD_QUAD)
+Use hardware quad FP instructions
+
+msoft-quad-float
+Target Report RejectNegative InverseMask(HARD_QUAD)
+Do not use hardware quad fp instructions
+
+mv8plus
+Target Report Mask(V8PLUS)
+Compile for V8+ ABI
+
+mvis
+Target Report Mask(VIS)
+Use UltraSPARC Visual Instruction Set extensions
+
+mptr64
+Target Report RejectNegative Mask(PTR64)
+Pointers are 64-bit
+
+mptr32
+Target Report RejectNegative InverseMask(PTR64)
+Pointers are 32-bit
+
+m64
+Target Report RejectNegative Mask(64BIT)
+Use 64-bit ABI
+
+m32
+Target Report RejectNegative InverseMask(64BIT)
+Use 32-bit ABI
+
+mstack-bias
+Target Report Mask(STACK_BIAS)
+Use stack bias
+
+mfaster-structs
+Target Report Mask(FASTER_STRUCTS)
+Use structs on stronger alignment for double-word copies
+
+mrelax
+Target
+Optimize tail call instructions in assembler and linker
+
+mcpu=
+Target RejectNegative Joined
+Use features of and schedule code for given CPU
+
+mtune=
+Target RejectNegative Joined
+Schedule code for given CPU
+
+mcmodel=
+Target RejectNegative Joined
+Use given SPARC-V9 code model
+
+
+Mask(LITTLE_ENDIAN)
+;; Generate code for little-endian
+
+Mask(LONG_DOUBLE_128)
+;; Use 128-bit long double
+
+Mask(SPARCLITE)
+;; Generate code for SPARClite
+
+Mask(SPARCLET)
+;; Generate code for SPARClet
+
+Mask(V8)
+;; Generate code for SPARC-V8
+
+Mask(V9)
+;; Generate code for SPARC-V9
+
+Mask(DEPRECATED_V8_INSNS)
+;; Generate code that uses the V8 instructions deprecated
+;; in the V9 architecture.